用于诊断量子比特的单层MOS量子点的开发。

IF 1.5 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Yanxue Hong, A N Ramanayaka, Ryan Stein, M D Stewart, J M Pomeroy
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引用次数: 0

摘要

介绍了抗介电击穿的单金属栅层、金属氧化物半导体(MOS)量子点器件的设计、制造和表征,作为未来诊断量子比特的原型。这些设备的开发是为了实现量子比特平台的长期目标的初步解决方案,用于材料之间的相互比较或在线诊断,并为建立预测相干性能的经典测量提供测试平台。在这个阶段,我们寻求一种强大的MOS设计,它与晶圆和芯片架构兼容,降低了工艺开销,并有足够的能力挑战和提高我们的测量能力。在本报告中,我们展示了使用单栅极层的第一批硅MOS器件,该器件在栅极电压漂移> 10 V时没有表现出任何故障,但确实表现出单栅极层设计所期望的静电控制降低。我们观察到量子点的形成,通道之间的电容电荷传感,以及能够进行自旋量子比特研究的合理有效电子温度。将讨论器件性能和制造效率之间权衡的成本和收益,以及未来改进的机会。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Developing Single Layer MOS Quantum Dots for Diagnostic Qubits.

The design, fabrication and characterization of single metal gate layer, metal-oxide-semiconductor (MOS) quantum dot devices robust against dielectric breakdown are presented as prototypes for future diagnostic qubits. These devices were developed as a preliminary solution to a longer term goal of a qubit platform for intercomparison between materials or for in-line diagnostics, and to provide a testbed for establishing classical measurements predictive of coherence performance. For this stage, we seek a robust MOS design that is compatible with wafer and chip architectures, that has a reduced process overhead and is sufficiently capable of challenging and advancing our measurement capabilities. In this report, we present our initial batch of silicon MOS devices using a single gate layer, which have not exhibited any failures with gate voltage excursions > 10 V, but do exhibit the reduced electrostatic control expected of a single gate layer design. We observe quantum dot formation, capacitive charge sensing between channels, and reasonable effective electron temperatures that enable spin qubit studies. The costs and benefits of the trade-off between device performance and fabrication efficiency will be discussed, as well as opportunities for future improvements.

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来源期刊
CiteScore
2.70
自引率
0.00%
发文量
146
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