1.7 kv 4H-SiC VDMOSFET单事件烧毁可靠性仿真研究

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2022-07-04 DOI:10.1109/TDMR.2022.3188235

Jia-Hao Luo;Ying Wang;Meng-Tian Bao;Xing-Ji Li;Jian-Qun Yang;Fei Cao

{"title":"1.7 kv 4H-SiC VDMOSFET单事件烧毁可靠性仿真研究","authors":"Jia-Hao Luo;Ying Wang;Meng-Tian Bao;Xing-Ji Li;Jian-Qun Yang;Fei Cao","doi":"10.1109/TDMR.2022.3188235","DOIUrl":null,"url":null,"abstract":"A single-event burnout (SEB) reliability and hardening method for 1.7-kV 4H-SiC power VDMOSFET under high liner energy transfer (LET) value range is proposed and researched by the 2-D numerical simulation. Compared with the conventional VDMOSFET with N-type multi-buffer layers, the hardened VDMOSFET not only ensures that the forward conduction capability does not deteriorate, but also reduces the peak electric field under breakdown voltage from 3.62 MV/cm to 2.98 MV/cm. The advantage of the hardened structure is providing a hole leakage path and increasing the contact area between the source metal and the N+ source, eliminating the effect of electron-hole pairs generated by heavy ion strike on the device, thus improving the SEB performance significantly. In addition, this fabricating technology is compatible with the current technological processes. This hardened structure provides a great potential in aerospace application.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"22 3","pages":"431-437"},"PeriodicalIF":2.5000,"publicationDate":"2022-07-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Simulation Study of Single-Event Burnout Reliability for 1.7-kV 4H-SiC VDMOSFET\",\"authors\":\"Jia-Hao Luo;Ying Wang;Meng-Tian Bao;Xing-Ji Li;Jian-Qun Yang;Fei Cao\",\"doi\":\"10.1109/TDMR.2022.3188235\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A single-event burnout (SEB) reliability and hardening method for 1.7-kV 4H-SiC power VDMOSFET under high liner energy transfer (LET) value range is proposed and researched by the 2-D numerical simulation. Compared with the conventional VDMOSFET with N-type multi-buffer layers, the hardened VDMOSFET not only ensures that the forward conduction capability does not deteriorate, but also reduces the peak electric field under breakdown voltage from 3.62 MV/cm to 2.98 MV/cm. The advantage of the hardened structure is providing a hole leakage path and increasing the contact area between the source metal and the N+ source, eliminating the effect of electron-hole pairs generated by heavy ion strike on the device, thus improving the SEB performance significantly. In addition, this fabricating technology is compatible with the current technological processes. This hardened structure provides a great potential in aerospace application.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"22 3\",\"pages\":\"431-437\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2022-07-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/9815213/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/9815213/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 1

摘要

提出了一种高线性能量传递(LET)值范围下1.7 kv 4H-SiC功率VDMOSFET的单事件烧断(SEB)可靠性和硬化方法，并通过二维数值模拟进行了研究。与具有n型多层缓冲层的传统VDMOSFET相比，硬化后的VDMOSFET不仅保证了正向导通能力不变差，而且击穿电压下的峰值电场从3.62 MV/cm降低到2.98 MV/cm。硬化结构的优点是提供了空穴泄漏路径，增加了源金属与N+源之间的接触面积，消除了重离子撞击对器件产生的电子-空穴对的影响，从而显著提高了SEB性能。此外，该制造技术与当前的工艺流程兼容。这种硬化结构在航空航天应用中具有很大的潜力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Simulation Study of Single-Event Burnout Reliability for 1.7-kV 4H-SiC VDMOSFET

A single-event burnout (SEB) reliability and hardening method for 1.7-kV 4H-SiC power VDMOSFET under high liner energy transfer (LET) value range is proposed and researched by the 2-D numerical simulation. Compared with the conventional VDMOSFET with N-type multi-buffer layers, the hardened VDMOSFET not only ensures that the forward conduction capability does not deteriorate, but also reduces the peak electric field under breakdown voltage from 3.62 MV/cm to 2.98 MV/cm. The advantage of the hardened structure is providing a hole leakage path and increasing the contact area between the source metal and the N+ source, eliminating the effect of electron-hole pairs generated by heavy ion strike on the device, thus improving the SEB performance significantly. In addition, this fabricating technology is compatible with the current technological processes. This hardened structure provides a great potential in aerospace application.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.