Unveiling the output conductance dynamics in Nanosheet FET: Does cryogenic temperature Make a Difference?

Channel length modulation (CLM) and drain-induced barrier lowering (DIBL) are well-known short-channel effects that result in a finite output conductance (g_ds). In a simplified analysis, g_ds is predominantly governed by the drain voltage (V_DS) and can be approximated by the slope of the I_DS–V_DS characteristics in the saturation regime. However, will the conceptual governance of g_ds be the same at the cryogenic temperatures? To answer this question, we thoroughly investigate the Cryogenic Nanosheet FET (NSFET) using well-calibrated TCAD models. The results reveal that incomplete ionization in the cryogenic temperature (CT) regime provides additional expansion of the depletion at the drain side. This significantly increases g_ds (i.e., the slope of the IDS-VDS characteristics) in CT compared to that at room temperature (RT). Therefore, in a Cryogenic FET, CLM becomes the function of temperature. Further, we extracted the CLM parameter (λ), early voltage (V_A), and intrinsic gain (g_max/g_ds) of the Nanosheet FET with varying temperatures and found that the g_max/g_ds is maximum at 4 K.