Reducing Warpage for Polymer-Based Embedded Silicon Fan-Out (P-eSiFO) Packaging During Thermal Process Loadings

Polymer-based embedded silicon-based fan-out (P-eSiFO) is a new packaging technique, which provides a way to high-density integration of high-performance chiplets. However, integrating multiple materials with diverse physical properties in the P-eSiFO leads to substantial warpage during downstream high-temperature manufacturing processes. In this study, a thermomechanical model of a P-eSiFO was developed to examine the thermomechanical with varying structural parameters and material selections. Test dies having an area of 0.5 cm² were embedded in a 500- $\mu $ m-thick silicon carrier following the P-eSiFO process. After careful parameters, optimization chip warpage can effectively decrease by over 60%. Experimental results showed that the height difference between the embedded chip and its silicon interposer can be reduced down to $1~\mu $ m with optimized parameters after high-temperature processes. This work provides useful insights for addressing multimaterial warpage concerns during thermal processes in advanced packaging.