Open Model Interface Assisted NBTI-Aware Design With Dual-Vth Logic Synthesis Strategy for Reliability Improvement

As CMOS technology scales down into the nanometer regime, the NBTI effect becomes a major issue for circuit reliability. This paper proposes an NBTI-aware design method with dual-Vth logic synthesis strategy for reliability improvement. NBTI awareness is innovatively incorporated into EDA toolchains based on NBTI-aware standard cell library and Open Model Interface (OMI), which considers aging difference among transistors instead of constant worst-case degradation. Furthermore, the circuit timing for post-aging delay is optimized by realizing the dual-Vth synthesis. The results show that in the original design without the optimal design strategy, the NBTI effect leads to obvious timing degradation. In contrast, when using the proposed OMI assisted design approach, timing degradation caused by NBTI can be suppressed effectively, allowing the circuit to continue operating normally even after aging.