相粗化对锡铋焊料互连不均匀变形和断裂行为的影响

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Shuibao Liang;Han Jiang;Zhihong Zhong;Yaohua Xu;Saranarayanan Ramachandran
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引用次数: 0

摘要

随着对人工智能、大数据等新兴技术的需求不断增加,先进的芯片集成和封装的重要性大大增加。锡铋基钎料在多层堆叠封装中得到了广泛的关注和探索,但其在使用过程中容易出现明显的粗化,晶粒和相各向异性的影响变得更加明显。这些因素都会影响锡铋焊料互连的性能和可靠性。本研究建立了一个数值模型来研究锡铋凸点互连的微观组织粗化,重点研究其对力学行为和裂纹扩展的影响。模拟的粗化行为与实验观察相符。结果表明:剪切载荷作用下,富sn相初始应力较大,富bi相后期应力较大,应力主要集中在富bi相或相界面处;热老化加剧了应力分布的不均匀性。富锡相的塑性应变较大,裂纹主要在富铋相萌生和扩展。粗化加速裂纹扩展,影响应力-应变响应。本研究提供了相粗化和不均匀变形对锡铋焊料互连的影响,这可能有助于三维封装互连设计和可靠性分析。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Influence of Phase Coarsening on Inhomogeneous Deformation and Fracture Behavior in Sn–Bi Solder Interconnects
With the increasing demand for emerging technologies like artificial intelligence and big data, the significance of advanced chip integration and packaging has grown considerably. Sn-Bi based solders have gained significant attention and have been explored for multi-layer stacked packaging, but they are prone to significant coarsening during service, and the effects of grain and phase anisotropy become more pronounced. These factors impact the performance and reliability of Sn-Bi solder interconnects. This study develops a numerical model to investigate microstructure coarsening in Sn-Bi solder bump interconnects, focusing on its effect on mechanical behavior and crack propagation. The simulated coarsening behavior aligns with experimental observations. Results show that, under shear loading, the Sn-rich phase experiences higher stress initially, while the Bi-rich phase bears greater stress later, leading to stress concentrations mainly in the Bi-rich phase or at the phase interfaces. Thermal aging exacerbates the uneven distribution of stress. Plastic strain is greater in the Sn-rich phase, and cracks primarily initiate and propagate in the Bi-rich phase. Coarsening accelerates crack growth, affecting the stress-strain response. This study provides insights into the effects of phase coarsening and inhomogeneous deformation in Sn-Bi solder interconnects, which may contribute to interconnect design and reliability analysis in three-dimensional packaging.
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来源期刊
IEEE Transactions on Device and Materials Reliability
IEEE Transactions on Device and Materials Reliability 工程技术-工程:电子与电气
CiteScore
4.80
自引率
5.00%
发文量
71
审稿时长
6-12 weeks
期刊介绍: The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.
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