底部通道覆盖率对亚1nm节点GAA Si NS cfet电特性的影响

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-09-08 DOI:10.1016/j.sse.2025.109244

Min-Hui Chuang , Sekhar Reddy Kola , Yiming Li

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引用次数: 0

摘要

本研究考察了底部寄生通道覆盖率对栅极全硅纳米片互补场效应管（GAA Si NS cfet）电特性的影响，该互补场效应管优化用于亚1nm技术节点。在n on p和p on n堆叠两种配置下，分析了覆盖率，范围从60%到100%。结果显示，覆盖率与底部器件泄漏电流之间存在很强的负相关关系：60%覆盖率的器件的泄漏电流比完全（100%）覆盖率的器件的泄漏电流大169倍（p on n）和140倍（n on p）。此外，共源放大器的高频特性表明，在100%底通道覆盖率的设备中，截止频率显著提高，突出了底通道完整性在模拟性能中的关键作用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of bottom channel coverage ratio on electrical characteristics of GAA Si NS CFETs for Sub-1-nm nodes

This study examines the impact of the bottom parasitic channel coverage ratio on the electrical characteristics of gate-all-around silicon nanosheet complementary FETs (GAA Si NS CFETs) optimized for sub-1-nm technology nodes. The coverage ratio, ranging from 60% to 100%, is analyzed in both n on p and p on n stacked configurations. Results reveal a strong inverse correlation between coverage ratio and bottom-device leakage current: devices with 60% coverage exhibit leakage currents up to 169× (p on n) and 140× (n on p) greater than those with full (100%) coverage. Additionally, the high-frequency behavior of a common-source amplifier shows that the cut-off frequency significantly improves in devices with a 100% bottom channel coverage ratio, highlighting the critical role of bottom-channel integrity in analog performance.

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.