Optimization of lateral source/drain growth profile for improving RC delay in nanosheet field-effect transistor

In the advancing sub-3 nm technology node, device evolution has progressed from FinFET to gate-all-around based nanosheet architectures (NSFETs). This transition addresses the limitations of FinFETs, where scaling down leads to a reduced number of fins, maintaining a quantized width and resulting in decreased current drivability. In contrast, NSFETs offer flexible width design similar to traditional planar structures and allow for multi-channel stacking, increasing current and making them an attractive candidate from a circuit design perspective. However, NSFETs also faces challenges in device performance due to increased parasitic RC components, despite improved gate controllability.

In this work, we analyzed parasitic RC components in NSFETs with different source/drain growth profiles using 3D TCAD simulations and then examined the RC delay to determine the source/drain growth profile that exhibits optimal device performance. Furthermore, we investigated self-heating effects (SHEs) to evaluate heat dissipation across different source/drain profiles, integrating these findings with RC delay analyses to propose the optimal growth profile.