A 3 nm IRDS projection based design space variability and experimental feasibility in junctionless forksheet FET: implications for next-generation digital, analog/RF, and circuit applications

This article explores the digital and analog/RF figures of merit (FOMs), and circuit performances for finding the optimal design space targeted at sub-3 nm technology node for the Junctionless Forksheet FET (JL FS-FET). Within the sub-3 nm node, the gate length (L_g), width (W_FS), and thickness (T_FS) are varied between 6 nm–14 nm, 20 nm–40 nm, and 5 nm–9 nm respectively. An optimal design space of L_g = 6 nm − 12 nm can be chosen for digital and analog/RF applications in the sub-3 nm technology node and scaling of L_g > 12 nm is not suitable for designed JL-FSFET since it gives deteriorated A_v and f_T which are the primary performance metrics to boost the device performance. Additionally, lowering the W_FS and T_FS is an optimal choice for improving the digital and analog performance whereas higher W_FS and T_FS should be opted for better RF performance in the sub-3 nm technology node. Moreover, stacking the sheets is a good idea to enhance the analog/RF performance at the cost of compromised A_v whereas an improper choice for digital performance. Further, the JL-FSFET based CMOS inverter layout cell for the optimal dimensions (L_g = 12 nm, T_FS = 5 nm, W_FS = 20 nm) provided better noise margins, gain of ∼9.82 V/V, and delay of ∼5.8 ps making the designed device to be adopted into digital ICs. These findings suggest that design space at sub-3 nm node hold significant potential for optimizing JL-FSFET performance for future device and circuit development.