Y. Du;Y. K. Zhang;H. L. Zhu;B. H. Wang;Q. Wang;W. L. Liu;Z. C. Wang;T. R. Luo;S. S. Lu;P. H. Sun;X. Y. Chen;Y. T. Zheng;H. Yang;J. J. Li;J. F. Li;X. L. Wang;J. Luo;W. W. Wang;B. W. Dai;T. C. Ye
{"title":"新型双面工艺实现互补垂直场效应管(cvfet)","authors":"Y. Du;Y. K. Zhang;H. L. Zhu;B. H. Wang;Q. Wang;W. L. Liu;Z. C. Wang;T. R. Luo;S. S. Lu;P. H. Sun;X. Y. Chen;Y. T. Zheng;H. Yang;J. J. Li;J. F. Li;X. L. Wang;J. Luo;W. W. Wang;B. W. Dai;T. C. Ye","doi":"10.1109/LED.2025.3587989","DOIUrl":null,"url":null,"abstract":"We demonstrated the monolithically integrated complementary vertical-channel field-effect-transistor (CVFET) inverters with an innovative dual-side process (DSP). Good electrical characteristics for both NMOS and PMOS were achieved: transconductance of <inline-formula> <tex-math>$69~\\mu $ </tex-math></inline-formula>S/<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>${\\mathrm{I}}_{\\text {on}} = 18~\\mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m (@ VGS – <inline-formula> <tex-math>${\\mathrm{V}}_{\\text {T}} =0.45$ </tex-math></inline-formula> V, <inline-formula> <tex-math>${\\mathrm{V}}_{\\text {DD}}=0.65$ </tex-math></inline-formula> V), Ion/<inline-formula> <tex-math>${\\mathrm{I}}_{\\text {off}} = 3.1\\times 10^{{6}}$ </tex-math></inline-formula>, SS =69 mV/dec and DIBL =12 mV/V for the top NMOS, and transconductance of <inline-formula> <tex-math>$592~\\mu $ </tex-math></inline-formula>S/<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>${\\mathrm{I}}_{\\text {on}} = 136~\\mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$\\mu $ </tex-math></inline-formula>m (@ VGS – <inline-formula> <tex-math>${\\mathrm{V}}_{\\text {T}} = -0.45$ </tex-math></inline-formula> V, <inline-formula> <tex-math>${\\mathrm{V}}_{\\text {DD}}= -0.65$ </tex-math></inline-formula> V), Ion/<inline-formula> <tex-math>${\\mathrm{I}}_{\\text {off}} = 5.4\\times 10^{{6}}$ </tex-math></inline-formula>, SS =72 mV/dec and DIBL=18 mV/V for the bottom PMOS. The functional CVFET inverters show well-balanced voltage transfer characteristics (VTC) up to 1.2 V with a maximum gain of 13 V/V. Furthermore, the CVFETs also featured with crystal-Si vertical channels and common self-aligned high-<inline-formula> <tex-math>$\\kappa $ </tex-math></inline-formula> metal gates. The CVFET structure and its integration scheme are strong candidates for the applications of advanced logic technologies.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 9","pages":"1473-1476"},"PeriodicalIF":4.5000,"publicationDate":"2025-07-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Complementary Vertical FETs (CVFETs) Enabled by a Novel Dual-Side Process\",\"authors\":\"Y. Du;Y. K. Zhang;H. L. Zhu;B. H. Wang;Q. Wang;W. L. Liu;Z. C. Wang;T. R. Luo;S. S. Lu;P. H. Sun;X. Y. Chen;Y. T. Zheng;H. Yang;J. J. Li;J. F. Li;X. L. Wang;J. Luo;W. W. Wang;B. W. Dai;T. C. Ye\",\"doi\":\"10.1109/LED.2025.3587989\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We demonstrated the monolithically integrated complementary vertical-channel field-effect-transistor (CVFET) inverters with an innovative dual-side process (DSP). Good electrical characteristics for both NMOS and PMOS were achieved: transconductance of <inline-formula> <tex-math>$69~\\\\mu $ </tex-math></inline-formula>S/<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>${\\\\mathrm{I}}_{\\\\text {on}} = 18~\\\\mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m (@ VGS – <inline-formula> <tex-math>${\\\\mathrm{V}}_{\\\\text {T}} =0.45$ </tex-math></inline-formula> V, <inline-formula> <tex-math>${\\\\mathrm{V}}_{\\\\text {DD}}=0.65$ </tex-math></inline-formula> V), Ion/<inline-formula> <tex-math>${\\\\mathrm{I}}_{\\\\text {off}} = 3.1\\\\times 10^{{6}}$ </tex-math></inline-formula>, SS =69 mV/dec and DIBL =12 mV/V for the top NMOS, and transconductance of <inline-formula> <tex-math>$592~\\\\mu $ </tex-math></inline-formula>S/<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m, <inline-formula> <tex-math>${\\\\mathrm{I}}_{\\\\text {on}} = 136~\\\\mu $ </tex-math></inline-formula>A/<inline-formula> <tex-math>$\\\\mu $ </tex-math></inline-formula>m (@ VGS – <inline-formula> <tex-math>${\\\\mathrm{V}}_{\\\\text {T}} = -0.45$ </tex-math></inline-formula> V, <inline-formula> <tex-math>${\\\\mathrm{V}}_{\\\\text {DD}}= -0.65$ </tex-math></inline-formula> V), Ion/<inline-formula> <tex-math>${\\\\mathrm{I}}_{\\\\text {off}} = 5.4\\\\times 10^{{6}}$ </tex-math></inline-formula>, SS =72 mV/dec and DIBL=18 mV/V for the bottom PMOS. The functional CVFET inverters show well-balanced voltage transfer characteristics (VTC) up to 1.2 V with a maximum gain of 13 V/V. Furthermore, the CVFETs also featured with crystal-Si vertical channels and common self-aligned high-<inline-formula> <tex-math>$\\\\kappa $ </tex-math></inline-formula> metal gates. The CVFET structure and its integration scheme are strong candidates for the applications of advanced logic technologies.\",\"PeriodicalId\":13198,\"journal\":{\"name\":\"IEEE Electron Device Letters\",\"volume\":\"46 9\",\"pages\":\"1473-1476\"},\"PeriodicalIF\":4.5000,\"publicationDate\":\"2025-07-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Electron Device Letters\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11077411/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11077411/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Complementary Vertical FETs (CVFETs) Enabled by a Novel Dual-Side Process
We demonstrated the monolithically integrated complementary vertical-channel field-effect-transistor (CVFET) inverters with an innovative dual-side process (DSP). Good electrical characteristics for both NMOS and PMOS were achieved: transconductance of $69~\mu $ S/$\mu $ m, ${\mathrm{I}}_{\text {on}} = 18~\mu $ A/$\mu $ m (@ VGS – ${\mathrm{V}}_{\text {T}} =0.45$ V, ${\mathrm{V}}_{\text {DD}}=0.65$ V), Ion/${\mathrm{I}}_{\text {off}} = 3.1\times 10^{{6}}$ , SS =69 mV/dec and DIBL =12 mV/V for the top NMOS, and transconductance of $592~\mu $ S/$\mu $ m, ${\mathrm{I}}_{\text {on}} = 136~\mu $ A/$\mu $ m (@ VGS – ${\mathrm{V}}_{\text {T}} = -0.45$ V, ${\mathrm{V}}_{\text {DD}}= -0.65$ V), Ion/${\mathrm{I}}_{\text {off}} = 5.4\times 10^{{6}}$ , SS =72 mV/dec and DIBL=18 mV/V for the bottom PMOS. The functional CVFET inverters show well-balanced voltage transfer characteristics (VTC) up to 1.2 V with a maximum gain of 13 V/V. Furthermore, the CVFETs also featured with crystal-Si vertical channels and common self-aligned high-$\kappa $ metal gates. The CVFET structure and its integration scheme are strong candidates for the applications of advanced logic technologies.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.