Stress in Single- and Multiribbon Complementary FETs (CFETs): Evolution in Process Flow and Impact on Drive Current

It is anticipated that strain engineering in nanosheet architectures, including complementary FETs (CFETs), will be challenging using conventional S/D epitaxy methods. This work investigates strain retention in CFETs through coupled mechanical and device simulations, offering integration-relevant suggestions for scalable strain engineering. A self-aligned process flow was simulated to identify stress-inducing steps: 1) S/D recess; 2) Si ${}_{{0}.{4}}$ Ge ${}_{{0}.{6}}$ S/D epitaxy; and 3) nanoribbon (NR) release. The final device is projected to retain 1.3-GPa (compressive) and +500-MPa (tensile) stress in the pMOS and nMOS channel, respectively. Even without S/D engineering, for nMOS, tensile channel stress arises due to strain imparted by the sacrificial layers (SLs), which also counteracts compressive stress in the pMOS channel. Consequently, Ge% in SLs is identified as a critical knob for tuning stress, as lowering it may enhance compressive stress in pMOS NRs, while employing different Ge% for nMOS/pMOS SLs could enable independent stress modulation. Furthermore, stress transfer in pMOS NRs is projected to rely on substrate anchoring of the S/D epi, thereby confining them to the bottom. The retained stress is predicted to remain unaffected by backside processing. Channel stress is also observed to scale with S/D volume, with multiribbon pMOS featuring increased compressive stress, albeit with 15%20% reduction in topmost ribbons. Simulated transfer characteristics estimate negligible drive current differences between (100)- and (110)-surfaces at high compressive stress ( $\ge 1$ GPa), while (110) remains favorable under lower stress. The simulations presented provide insights to guide technological choices for integrating strained channels in CFETs and outlines directions for experimental validation.