在无晶圆室中使用后涂层处理来减少缺陷和改善线宽粗糙度

IF 2.3 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Semiconductor Manufacturing Pub Date : 2025-02-13 DOI:10.1109/TSM.2025.3535145

Jeff J. Ye;Raviteja Pagadala;Fei Lu

{"title":"在无晶圆室中使用后涂层处理来减少缺陷和改善线宽粗糙度","authors":"Jeff J. Ye;Raviteja Pagadala;Fei Lu","doi":"10.1109/TSM.2025.3535145","DOIUrl":null,"url":null,"abstract":"Defect and line width roughness (LWR) are two main yield detractors in advanced plasma etch process in high-volume memory manufacturing. In this paper, we present the results of defect reduction and LWR improvement by using a post pre-coat treatment (PPT) method in waferless chamber clean (WCC) recipe. Adding a PPT step at the end of WCC recipe reduces defect, inline critical dimension (CD) variation and LWR. Atomic force microscopy (AFM) results show pre-coat silicon oxide and/or PPT improves surface roughness by 30%. X-ray photoelectron spectroscopy (XPS) has been utilized to characterize the surfaces treated with and without PPT, indicating PPT can remove residue chloride and solidify SiO2 film from its loose form. With the implementation of WCC with PPT, we have achieved yield improvement, which is attributed to defect reduction, tighter inline CD and LWR improvement.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 3","pages":"399-403"},"PeriodicalIF":2.3000,"publicationDate":"2025-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Defect Reduction and Line Width Roughness Improvement by Using a Post Precoat Treatment in Waferless Chamber Conditioning\",\"authors\":\"Jeff J. Ye;Raviteja Pagadala;Fei Lu\",\"doi\":\"10.1109/TSM.2025.3535145\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Defect and line width roughness (LWR) are two main yield detractors in advanced plasma etch process in high-volume memory manufacturing. In this paper, we present the results of defect reduction and LWR improvement by using a post pre-coat treatment (PPT) method in waferless chamber clean (WCC) recipe. Adding a PPT step at the end of WCC recipe reduces defect, inline critical dimension (CD) variation and LWR. Atomic force microscopy (AFM) results show pre-coat silicon oxide and/or PPT improves surface roughness by 30%. X-ray photoelectron spectroscopy (XPS) has been utilized to characterize the surfaces treated with and without PPT, indicating PPT can remove residue chloride and solidify SiO2 film from its loose form. With the implementation of WCC with PPT, we have achieved yield improvement, which is attributed to defect reduction, tighter inline CD and LWR improvement.\",\"PeriodicalId\":451,\"journal\":{\"name\":\"IEEE Transactions on Semiconductor Manufacturing\",\"volume\":\"38 3\",\"pages\":\"399-403\"},\"PeriodicalIF\":2.3000,\"publicationDate\":\"2025-02-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Semiconductor Manufacturing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10887004/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10887004/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

缺陷和线宽粗糙度（LWR）是影响大批量存储器制造中先进等离子蚀刻工艺成品率的两个主要因素。在本文中，我们介绍了在无晶圆室清洁（WCC）配方中使用后预涂层处理（PPT）方法减少缺陷和提高LWR的结果。在WCC配方的末尾添加PPT步骤可以减少缺陷、内联临界尺寸（CD）变化和LWR。原子力显微镜（AFM）结果显示，预涂氧化硅和/或PPT可使表面粗糙度提高30%。利用x射线光电子能谱（XPS）对PPT处理和未处理的表面进行了表征，表明PPT可以去除残留的氯化物，并使松散的SiO2膜固化。随着WCC与PPT的实施，我们实现了良率的提高，这归功于缺陷的减少，更紧密的内联CD和LWR的提高。

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Defect Reduction and Line Width Roughness Improvement by Using a Post Precoat Treatment in Waferless Chamber Conditioning

Defect and line width roughness (LWR) are two main yield detractors in advanced plasma etch process in high-volume memory manufacturing. In this paper, we present the results of defect reduction and LWR improvement by using a post pre-coat treatment (PPT) method in waferless chamber clean (WCC) recipe. Adding a PPT step at the end of WCC recipe reduces defect, inline critical dimension (CD) variation and LWR. Atomic force microscopy (AFM) results show pre-coat silicon oxide and/or PPT improves surface roughness by 30%. X-ray photoelectron spectroscopy (XPS) has been utilized to characterize the surfaces treated with and without PPT, indicating PPT can remove residue chloride and solidify SiO2 film from its loose form. With the implementation of WCC with PPT, we have achieved yield improvement, which is attributed to defect reduction, tighter inline CD and LWR improvement.

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来源期刊

IEEE Transactions on Semiconductor Manufacturing 工程技术-工程：电子与电气

CiteScore

5.20

自引率

11.10%

发文量

101

审稿时长

3.3 months

期刊介绍： The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.