数字低压差稳压器辅助降压DC-DC变换器，降压电压为68 mv，效率为95.5%

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-06-20 DOI:10.1109/LSSC.2025.3581844

Yichen Xu;Zhaoqing Wang;Rentao Wan;Suhwan Kim;Minxiang Gong;Ram Krishnamurthy;Xin Zhang;Mingoo Seok

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引用次数: 0

摘要

本文提出了一种数字低差调节器（DLDO）辅助降压转换器，具有一步计算下垂补偿和DLDO反馈控制的电流切换。28nm测试芯片在1A/0.8ns负载阶跃下实现了68 mv的下垂电压和112 ns的稳定时间，同时保持了95.5%的峰值效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Digital Low-Dropout Regulator-Assisted Buck DC-DC Converter Achieving 68-mV Droop Voltage and 95.5% Efficiency

This letter proposes a digital low-dropout regulator (DLDO)-assisted buck converter featuring one-step computational droop compensation and DLDO feedback-controlled current handover. The 28-nm test chip achieves a 68-mV droop voltage and a 112-ns settling time for a 1A/0.8ns load step while maintaining a high-peak efficiency of 95.5%.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量