Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue
{"title":"具有高线路灵敏度和电源抑制比的p-GaN HEMT基准电压","authors":"Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue","doi":"10.1109/JEDS.2025.3588210","DOIUrl":null,"url":null,"abstract":"A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to <inline-formula> <tex-math>$250~{^{\\circ }}$ </tex-math></inline-formula>C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"630-637"},"PeriodicalIF":2.4000,"publicationDate":"2025-07-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078414","citationCount":"0","resultStr":"{\"title\":\"A p-GaN HEMT Voltage Reference With High Line Sensitivity and Power Supply Rejection Ratio\",\"authors\":\"Pingyu Cao;Kepeng Zhao;Yihao Xu;Harm Van Zalinge;Sang Lam;Ping Zhang;Miao Cui;Fei Xue\",\"doi\":\"10.1109/JEDS.2025.3588210\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to <inline-formula> <tex-math>$250~{^{\\\\circ }}$ </tex-math></inline-formula>C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.\",\"PeriodicalId\":13210,\"journal\":{\"name\":\"IEEE Journal of the Electron Devices Society\",\"volume\":\"13 \",\"pages\":\"630-637\"},\"PeriodicalIF\":2.4000,\"publicationDate\":\"2025-07-11\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11078414\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of the Electron Devices Society\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/11078414/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/11078414/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A p-GaN HEMT Voltage Reference With High Line Sensitivity and Power Supply Rejection Ratio
A monolithically integrated voltage reference based on p-GaN HEMT technology is demonstrated in this work. The proposed two-stage structure can improve the stability of the generated reference voltage over a wide range of the supply voltage and temperature. The static and dynamic performance was measured at various temperatures. Experimental results indicate that the output voltage is stable at 1.3 V when the supply voltage rises from 2.8 V to 40 V, with a line sensitivity of 0.035%/V at room temperature. When the measurement temperature increases to $250~{^{\circ }}$ C, the generated reference voltage slightly decreases to 1.25 V with a temperature coefficient of −22.1 ppm/°C. The power supply rejection ratio of this work is competitive, as the power supply rejection ratio changes from −46.64 dB to −56.2 dB, in which the noise frequency varies from 10 Hz to 5 MHz. The voltage variation of the generated reference voltage is relatively small when the frequency exceeds 5 MHz. The results show that the proposed work is particularly suitable for all-GaN monolithic integration circuits that require thermally stable bias voltages with high immunity to the supply voltage variation.
期刊介绍:
The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.