晶粒形貌对先进半导体封装中Cu-Cu键合界面空隙闭合的影响

IF 1.6 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Han Jiang , Yaohua Xu , Saranarayanan Ramachandran , Shuibao Liang
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引用次数: 0

摘要

在后摩尔时代对集成密度和异质集成的需求推动下,Cu-Cu直接键合已成为先进封装中实现细间距互连的关键技术。然而,由于界面空洞的存在和在键合过程中形成的复杂晶粒形态,实现可靠的键合仍然具有挑战性。本文建立了相场模型,并利用相场模型研究了Cu-Cu键合过程中晶粒形貌对界面空隙闭合动力学的影响。通过不同的晶粒尺寸和形貌,构建了具有代表性的构型,以模拟真实的微观结构场景。结果表明,结合结构两侧小晶粒数量越多,孔隙闭合速度越快,界面致密化程度越均匀;这种行为归因于晶界的增加,晶界作为增强的扩散途径通过界面。结合过程中应力场的演化表明,随着孔洞的闭合,应力场的分布更加均匀。在整个闭合过程中,孔洞区域附近的应力三轴性保持在−1以下,表明孔洞处于有利于消除的静水压缩状态。这些发现为进一步了解空隙闭合机制提供了基础,并可能为提高先进封装应用中Cu-Cu键合的可靠性提供有价值的指导。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Grain morphology effect on interfacial void closure in Cu–Cu bonding for advanced semiconductor packaging
Driven by the demands of increased integration density and heterogeneous integration in the post-Moore era, Cu–Cu direct bonding has become a critical technology for enabling fine-pitch interconnects in advanced packaging. However, achieving reliable bonds remains challenging due to the existence of interfacial voids and the complex grain morphology that develops during the bonding process. In this work, a phase field model is developed and employed to investigate the effect of grain morphology on the kinetics of interfacial void closure during the Cu–Cu bonding process. Representative configurations are constructed by varying grain size and morphology in both bonded Cu pads to simulate realistic microstructural scenario. The results show that configurations with a larger number of smaller grains on both sides of the bonding structures promote faster void closure and achieve more uniform interfacial densification. This behavior is attributed to the increased presence of grain boundaries, which serve as enhanced diffusion pathways across the interface. Furthermore, the evolution of stress fields during bonding indicates that stress becomes more evenly distributed as voids close. The stress triaxiality near void regions remains below −1 throughout the closure process, demonstrating a favorable hydrostatic compressive state for void elimination. These findings provide further fundamental understanding of the mechanisms of void closure and may offer valuable guidance for improving the reliability of Cu–Cu bonding in advanced packaging applications.
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来源期刊
Microelectronics Reliability
Microelectronics Reliability 工程技术-工程:电子与电气
CiteScore
3.30
自引率
12.50%
发文量
342
审稿时长
68 days
期刊介绍: Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.
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