Investigation of DFF cells SEU effect for 14 nm bulk silicon FinFET technology irradiated by heavy ions

A single-event effect test circuit was implemented in 14 nm bulk silicon FinFET technology, incorporating five flip-flop configurations: a standard D-type flip-flop (DFF), a logic depth DFF (LOG-DFF), a compact triple modular redundancy DFF (TMR-DFF), an interleaved TMR-DFF (INTER-TMR-DFF), and a dual interlocked storage cell DFF (DICE-DFF). Radiation testing was performed using heavy ion accelerator facilities with four ion species (F, Cl, Ge, and Ta). Experimental results demonstrated that the INTER-TMR-DFF achieved optimal single-event upset (SEU) resistance, although with area overhead, higher propagation delay, and greater power consumption compared to the baseline DFF. Both TMR-DFF and DICE-DFF exhibited effective radiation hardening at low linear energy transfer (LET) values, but showed degraded performance at higher LET levels. Notably, the DICE-DFF displayed a 40.7% increase in saturation cross-section relative to the standard DFF at LET values equal to 83.8 MeV·cm²/mg. This performance degradation under high-LET conditions correlates with technology scaling effects in advanced nanoscale processes: reduced feature sizes and increased transistor density exacerbate charge sharing phenomena. These parasitic charge redistribution effects fundamentally influence SEU mechanisms, compromising the radiation hardening benefits of both TMR-DFF and DICE-DFF architectures. Comprehensive comparative analysis evaluated all five flip-flop designs across multiple metrics: area occupation, propagation delay, power consumption, transistor count, and SEU resistance performance.