Engineered semiconductor-dielectric interfaces in polymer ferroelectric transistors†

Polymer ferroelectrics are witnessing a renewed interest in organic transistors due to their multi-conductance states. Although their high dielectric constant allows low operating voltages, the polarization fluctuation due to the energetic disorder at the interface reduces the carrier mobility in organic transistors. Here, two copolymers of poly(vinylidene fluoride) (PVDF) with trifluoroethylene (TrFE) and hexafluoropropylene (HFP) as the dielectric layer, and a donor–acceptor copolymer as the active semiconductor layer are used in bottom-gate top-contact transistor architectures. We investigate the impact of the dielectric thickness, external poling, and an added interfacial ultrathin Al₂O₃ layer at the semiconductor-dielectric surface on the performance of organic field-effect transistors (FETs). Although poling the dielectric layer significantly enhances the carrier mobility in PVDF-TrFE-based FETs, it has a minimal effect on PVDF-HFP-based devices. Poled PVDF-TrFE devices with a thickness of 45 nm show the highest saturation carrier mobility, exceeding 1 cm² V⁻¹ s⁻¹. The subthreshold swing (SS), which is primarily governed by the trap states at the semiconductor–dielectric interface, is seen to significantly improve when an atomic layer deposited Al₂O₃ film with varying thickness between 2 nm and 12 nm is deposited on PVDF-HFP. In the linear region of operation, PVDF-HFP based FETs with Al₂O₃ yield SS values below 80 mV dec⁻¹. The trap density of states at the semiconductor–dielectric interface was evaluated, providing deeper insight into charge trapping and transport mechanisms.