L. Donetti;C. Medina-Bailon;J. L. Padilla;C. Sampedro;F. Gamiz
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The capacitance of the gate oxide is a crucial parameter to model the performance of MOSFETs. The traditional expression used to compute it stems from the parallel-plate capacitor formula. While its use is appropriate for planar devices, it has been naturally extended to 3-D devices such as those based on nanosheets even if the geometry is quite different. In this work, we compute numerically the gate oxide capacitance of nanosheet transistors and, observing a nonnegligible discrepancy with the planar model, we propose a simple model that better reproduces the computed capacitance. Then, we investigate the definition of equivalent oxide thickness (EOT), showing that it cannot be strictly used for nonplanar devices: however, our improved model allows us to obtain a useful expression valid for the most common cases. Finally, we generalize the capacitance model to nanosheets with rounded corners.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.