Siyu Guo;Assaf Lahav;Quan Zhou;Pierre Boulenc;Alexander V. Klekachev;Xinjie Zhuang;Xinyang Wang
{"title":"低功耗和高速应用的TDI成像传感器像素设计","authors":"Siyu Guo;Assaf Lahav;Quan Zhou;Pierre Boulenc;Alexander V. Klekachev;Xinjie Zhuang;Xinyang Wang","doi":"10.1109/LED.2025.3556414","DOIUrl":null,"url":null,"abstract":"In this letter, a novel high-speed, low-power consumption, large full well capacity (FWC), charge-domain Time-Delay Integration (TDI) image sensor based on a 90nm CCD-in-CMOS process is presented. A combination of the advantages of the buried channel in the CCD channel and the pinning voltage gradient in the fully depleted tapered Pinned-Photodiode (PPD) makes the proposed new structure well-suited for low-power and high-speed applications. To demonstrate the effectiveness of both optimizations, a Back-Side Illumination (BSI) test chip with a <inline-formula> <tex-math>$14~\\mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$\\times 14~\\mu $ </tex-math></inline-formula>m pixel is designed, manufactured, and characterized. The pixel maximum FWC exceeds 120 ke−. Thanks to the built-in electric field in the tapered PPD, the test chip achieves 99.998% Charge Transfer Efficiency (CTE) under equivalent 2.5 MHz line frequency condition without Modulation Transfer Function (MTF) degradation.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"46 6","pages":"940-943"},"PeriodicalIF":4.5000,"publicationDate":"2025-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of TDI Imaging Sensor Pixel for Low Power Consumption and High-Speed Applications\",\"authors\":\"Siyu Guo;Assaf Lahav;Quan Zhou;Pierre Boulenc;Alexander V. Klekachev;Xinjie Zhuang;Xinyang Wang\",\"doi\":\"10.1109/LED.2025.3556414\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this letter, a novel high-speed, low-power consumption, large full well capacity (FWC), charge-domain Time-Delay Integration (TDI) image sensor based on a 90nm CCD-in-CMOS process is presented. A combination of the advantages of the buried channel in the CCD channel and the pinning voltage gradient in the fully depleted tapered Pinned-Photodiode (PPD) makes the proposed new structure well-suited for low-power and high-speed applications. To demonstrate the effectiveness of both optimizations, a Back-Side Illumination (BSI) test chip with a <inline-formula> <tex-math>$14~\\\\mu $ </tex-math></inline-formula>m <inline-formula> <tex-math>$\\\\times 14~\\\\mu $ </tex-math></inline-formula>m pixel is designed, manufactured, and characterized. The pixel maximum FWC exceeds 120 ke−. Thanks to the built-in electric field in the tapered PPD, the test chip achieves 99.998% Charge Transfer Efficiency (CTE) under equivalent 2.5 MHz line frequency condition without Modulation Transfer Function (MTF) degradation.\",\"PeriodicalId\":13198,\"journal\":{\"name\":\"IEEE Electron Device Letters\",\"volume\":\"46 6\",\"pages\":\"940-943\"},\"PeriodicalIF\":4.5000,\"publicationDate\":\"2025-03-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Electron Device Letters\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10946183/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10946183/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Design of TDI Imaging Sensor Pixel for Low Power Consumption and High-Speed Applications
In this letter, a novel high-speed, low-power consumption, large full well capacity (FWC), charge-domain Time-Delay Integration (TDI) image sensor based on a 90nm CCD-in-CMOS process is presented. A combination of the advantages of the buried channel in the CCD channel and the pinning voltage gradient in the fully depleted tapered Pinned-Photodiode (PPD) makes the proposed new structure well-suited for low-power and high-speed applications. To demonstrate the effectiveness of both optimizations, a Back-Side Illumination (BSI) test chip with a $14~\mu $ m $\times 14~\mu $ m pixel is designed, manufactured, and characterized. The pixel maximum FWC exceeds 120 ke−. Thanks to the built-in electric field in the tapered PPD, the test chip achieves 99.998% Charge Transfer Efficiency (CTE) under equivalent 2.5 MHz line frequency condition without Modulation Transfer Function (MTF) degradation.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.