191.5 dBc/Hz频率的串并联谐振振荡器

IF 2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2025-04-25 DOI:10.1109/LSSC.2025.3564312

Shiwei Zhang;Wei Deng;Haikun Jia;Hongzhuo Liu;Junlong Gong;Qiuyu Peng;Baoyong Chi

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引用次数: 0

摘要

为了实现稳健的超低相位噪声（PN）和高品质因数（FoM），本文提出了一种基于以下思想的串并联谐振振荡器拓扑：1)在紧凑的布局中支持高功耗和有效PN抑制的低阻抗谐振器；2)阻抗和增益提升，用于PN功率权衡，更锐利的过渡和主动降噪。该x波段振荡器采用65纳米CMOS技术原型，在1 mhz偏置时PN为- 131.4 dBc/Hz， FoM为191.5 dBc/Hz，在10 GHz正交输出时FoMA（即带面积的FoM）为198.5 dBc/Hz。

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A Series-Parallel-Resonance Oscillator With a 191.5 dBc/Hz FoM

To achieve robust ultra-low phase noise (PN) and a high figure of merit (FoM), this letter proposes a series-parallel-resonance oscillator topology based on the following ideas: 1) a low-impedance resonator that supports high power consumption and effective PN suppression within a compact layout and 2) impedance and gain boosting for PN-power tradeoff, sharper transition, and active noise reduction. Prototyped in 65-nm CMOS technology, the proposed X-band oscillator demonstrates a PN of −131.4 dBc/Hz at 1-MHz offset, a FoM of 191.5 dBc/Hz, and a FoMA (i.e., FoM with area) of 198.5 dBc/Hz at 10 GHz with quadrature output.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量