Yu Fang;I. Ciofi;Ph. J. Roussel;A. Lesniewska;V. M. Blanco Carballo;R. Degraeve;I. De Wolf;K. Croes
{"title":"BEOL TDDB的三维建模:sub - 20nm半间距互连的可变性规格","authors":"Yu Fang;I. Ciofi;Ph. J. Roussel;A. Lesniewska;V. M. Blanco Carballo;R. Degraeve;I. De Wolf;K. Croes","doi":"10.1109/TED.2025.3554474","DOIUrl":null,"url":null,"abstract":"A pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":"72 5","pages":"2165-2172"},"PeriodicalIF":2.9000,"publicationDate":"2025-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Three-Dimensional Modeling of BEOL TDDB: Variability Specs for Sub-20 nm Half-Pitch Interconnects\",\"authors\":\"Yu Fang;I. Ciofi;Ph. J. Roussel;A. Lesniewska;V. M. Blanco Carballo;R. Degraeve;I. De Wolf;K. Croes\",\"doi\":\"10.1109/TED.2025.3554474\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.\",\"PeriodicalId\":13092,\"journal\":{\"name\":\"IEEE Transactions on Electron Devices\",\"volume\":\"72 5\",\"pages\":\"2165-2172\"},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2025-04-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Electron Devices\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10952385/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10952385/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Three-Dimensional Modeling of BEOL TDDB: Variability Specs for Sub-20 nm Half-Pitch Interconnects
A pragmatic 2-step model of back-end-of-line (BEOL) time-dependent dielectric breakdown (TDDB) is proposed, which accounts for the complex 3-D features in BEOL interconnects. First, for each point in the dielectric, the metal-to-metal shortest straight percolation path (SSPP) is extracted and the related failure probability is computed. Finally, weakest-link statistics are applied to predict the reliability of the investigated interconnect scheme. This model is fit to TDDB measurements from low-k planar capacitors with different thickness to capture the dependence of the model parameters on the SSPP length. This model is applied to generate variability specs for meeting ten years lifetime at operating conditions for sub-20 nm half-pitch interconnects. As for variability sources, via misalignment (VM), tip-to-tip spacing variation, line-edge roughness (LER), and die-to-die spacing variation are considered. It is predicted that nominal line-to-line spacings of 7 nm can be reliable when extreme ultraviolet lithography (EUV) spacer-assisted multi patterning is used as a litho-patterning process. Moreover, this model shows that fully self-aligned via (FSAV) processes can enable nominal line-to-line spacings as small as 5 nm, as they can prevent via-to-line failures.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.