基于多物理场的机器学习辅助芯片布局异构集成

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Vinicius C. Do Nascimento;Seunghyun Hwang;Michael Joseph Smith;Tejas Kulkarni;Qiang Qiu;Cheng-Kok Koh;Ganesh Subbarayan;Dan Jiao
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引用次数: 0

摘要

异构集成系统级封装(sip)中小芯片的平面设计必须考虑多物理场(电、热、机械)性能,并在优化过程中满足位置约束。本文提出了一个基于位置和多物理场性能约束的芯片地板规划的有效框架。传统的多物理场模拟由于计算成本高而难以优化,通过基于图像的机器学习(ML),取代了高保真、高效的条件图像生成模型。该模型是准确的,能够在整个三维sip中进行多物理场性能的实时预测。利用基于图像的机器学习模型进行快速性能评估,我们通过开发一种新的、高度并行的动态秩揭示(RR)算法来解决潜在的约束优化问题,进一步加速了物理设计。我们利用该算法直接优化受多物理场性能影响的小芯片的位置,而无需平面图表示或凸化技术,同时满足多种约束。在模拟退火(SA)优化框架下,相同的ML模型和约束也集成到最先进的角块列表(CBL)平面图表示中。本文提出的优化方法的准确性和效率在受热约束的中间体上芯片的平面规划中得到了证明,并与ml辅助的SA-CBL进行了比较,以执行相同的任务。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Multiphysics-Informed ML-Assisted Chiplet Floorplanning for Heterogeneous Integration
The floorplan of chiplets in heterogeneously integrated systems-in-package (SiPs) must consider multiphysics (electrical, thermal, and mechanical) performance and meet positional constraints during optimization. This article sets forth an efficient framework for chiplet floorplanning subject to positional and multiphysics-performance-based constraints. Traditional multiphysics simulations, often impractical in optimization due to high computational cost, are replaced by a high-fidelity and efficient conditional image generative model via image-based machine learning (ML). This model is accurate and capable of performing real-time prediction of multiphysics performance throughout 3-D SiPs. Utilizing the image-based ML model for fast performance assessment, we further accelerate the physical design by developing a novel and highly parallelizable dynamic rank-revealing (RR) algorithm for solving the underlying constrained optimization problem. We leverage this algorithm to optimize the position of the chiplets subject to multiphysics performance directly without floorplan representation or convexification techniques while meeting a multitude of constraints. The same ML model and constraints are also integrated into a state-of-the-art corner block list (CBL) floorplan representation under a simulated annealing (SA) optimization framework. The accuracy and efficiency of the proposed optimization method are demonstrated in the floorplanning of chiplets on an interposer subject to thermal constraints, and by comparisons against ML-assisted SA-CBL for performing the same task.
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来源期刊
IEEE Transactions on Components, Packaging and Manufacturing Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
4.70
自引率
13.60%
发文量
203
审稿时长
3 months
期刊介绍: IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.
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