自封装紧凑型滤波器阵列:基于改进基板集成悬浮线技术的创新

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef
{"title":"自封装紧凑型滤波器阵列:基于改进基板集成悬浮线技术的创新","authors":"Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef","doi":"10.1109/TCPMT.2025.3554181","DOIUrl":null,"url":null,"abstract":"This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1025-1031"},"PeriodicalIF":2.3000,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Self-Packaged Compact Filter Array: Innovations Based on Modified Substrate Integrated Suspension Line Technology\",\"authors\":\"Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef\",\"doi\":\"10.1109/TCPMT.2025.3554181\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.\",\"PeriodicalId\":13085,\"journal\":{\"name\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"volume\":\"15 5\",\"pages\":\"1025-1031\"},\"PeriodicalIF\":2.3000,\"publicationDate\":\"2025-03-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10938295/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10938295/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

本文介绍了一种设计自封装滤波器阵列的新方法,该方法将两个带通滤波器(bpf)集成到衬底集成悬浮线(SISL)平台上。本设计中采用的创新拓扑为每个滤波电路建立了单独的气腔,通过分层多个基板层并在两端封装接地基板来创建。所有滤波器输入和输出端口位于底部接平面上,并通过金属引脚和多层基板连接到各自的端口。为了解决阻抗匹配问题并减轻金属引脚连接产生的寄生效应,在引脚与微带线连接处实施了策略阻抗匹配技术。此外,垂直互连通道(VIA)结构战略性地定位在空腔的外围,连接所有基板层的接地面。与传统的SISL结构相比,这种设计创新减少了两个空腔,有效地减小了体积,缩短了连接引脚长度,从而简化了阻抗匹配过程。该设计实现了四平无引线(QFN)封装风格,将每个滤波电路封装在包含接地面、过孔以及上下接地面的多层基板上。通过测量两个bpf,对所提出的包装设计概念进行了实验验证,结果表明所提出的包装模式提高了过滤器的性能,特别是在减少损失方面。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Self-Packaged Compact Filter Array: Innovations Based on Modified Substrate Integrated Suspension Line Technology
This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.
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来源期刊
IEEE Transactions on Components, Packaging and Manufacturing Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
4.70
自引率
13.60%
发文量
203
审稿时长
3 months
期刊介绍: IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.
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