Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef
{"title":"自封装紧凑型滤波器阵列:基于改进基板集成悬浮线技术的创新","authors":"Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef","doi":"10.1109/TCPMT.2025.3554181","DOIUrl":null,"url":null,"abstract":"This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.","PeriodicalId":13085,"journal":{"name":"IEEE Transactions on Components, Packaging and Manufacturing Technology","volume":"15 5","pages":"1025-1031"},"PeriodicalIF":2.3000,"publicationDate":"2025-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Self-Packaged Compact Filter Array: Innovations Based on Modified Substrate Integrated Suspension Line Technology\",\"authors\":\"Tao Tang;Runlin Zhang;Maged A. Aldhaeebi;Thamer S. Almoneef\",\"doi\":\"10.1109/TCPMT.2025.3554181\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.\",\"PeriodicalId\":13085,\"journal\":{\"name\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"volume\":\"15 5\",\"pages\":\"1025-1031\"},\"PeriodicalIF\":2.3000,\"publicationDate\":\"2025-03-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Components, Packaging and Manufacturing Technology\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10938295/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Components, Packaging and Manufacturing Technology","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10938295/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Self-Packaged Compact Filter Array: Innovations Based on Modified Substrate Integrated Suspension Line Technology
This article introduces a novel approach to designing a self-packaged filter array by integrating two bandpass filters (BPFs) onto a substrate integrated suspended line (SISL) platform. The innovative topology employed in this design establishes individual air cavities for each filter circuit, created by layering multiple substrate layers and packaging them with grounded substrates at both ends. All filter input and output ports are situated on the bottom ground plane and are connected to their respective ports via metal pins and a multilayer substrate. To address impedance-matching challenges and mitigate parasitic effects resulting from the metal pin connections, strategic impedance-matching techniques are implemented at the pin-to-microstrip line junctions. Furthermore, vertical interconnect access (VIA) structures are strategically positioned around the periphery of the air cavities, linking the ground planes of all substrate layers. This design innovation reduces the number of air cavities by two compared to conventional SISL structures, effectively minimizing volume and shortening connection pin lengths, thereby simplifying the impedance-matching process. The design achieves a quad-flat no-leads (QFN) packaging style by encapsulating each filter circuit with a multilayer substrate containing ground planes, VIAs, and top and bottom ground layers. Validation of the proposed packaging design concept is conducted experimentally through the measurement of two BPFs, with results indicating that the proposed packaging mode enhances filter performance, particularly in terms of reducing losses.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.