{"title":"基于柔性交货期优化模型的半导体晶圆制造设备产能评估","authors":"Sungwon Hong;Younsoo Lee;Kyungsik Lee","doi":"10.1109/TSM.2025.3547026","DOIUrl":null,"url":null,"abstract":"In this paper, we consider the problem of production capacity estimation for a semiconductor wafer fabrication facility. Capacity estimation involves determining the maximum achievable throughput of a wafer fabrication facility during a given planning horizon in consideration of both product mix and target cycle time. The wafer fabrication facility (fab) is one of the most complex production systems, consisting of hundreds of process steps for each product as well as thousands of processing machines and re-entrant process flows wherein products must visit the same workcenter multiple times. In this regard, estimating production capacity by modeling the wafer manufacturing process is a challenging problem. To properly capture the dynamics of the process, we propose a flexible-lead-time-based optimization model that considers both the state of work-in-process (WIP) over time and the relationship between WIP levels and lead times. The results of simulation experiments using a real-sized instance demonstrate the advantages of the proposed model over existing alternatives.","PeriodicalId":451,"journal":{"name":"IEEE Transactions on Semiconductor Manufacturing","volume":"38 2","pages":"292-310"},"PeriodicalIF":2.3000,"publicationDate":"2025-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Capacity Estimation for Semiconductor Wafer Fabrication Facilities via an Optimization Model Based on Flexible Lead Times\",\"authors\":\"Sungwon Hong;Younsoo Lee;Kyungsik Lee\",\"doi\":\"10.1109/TSM.2025.3547026\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we consider the problem of production capacity estimation for a semiconductor wafer fabrication facility. Capacity estimation involves determining the maximum achievable throughput of a wafer fabrication facility during a given planning horizon in consideration of both product mix and target cycle time. The wafer fabrication facility (fab) is one of the most complex production systems, consisting of hundreds of process steps for each product as well as thousands of processing machines and re-entrant process flows wherein products must visit the same workcenter multiple times. In this regard, estimating production capacity by modeling the wafer manufacturing process is a challenging problem. To properly capture the dynamics of the process, we propose a flexible-lead-time-based optimization model that considers both the state of work-in-process (WIP) over time and the relationship between WIP levels and lead times. The results of simulation experiments using a real-sized instance demonstrate the advantages of the proposed model over existing alternatives.\",\"PeriodicalId\":451,\"journal\":{\"name\":\"IEEE Transactions on Semiconductor Manufacturing\",\"volume\":\"38 2\",\"pages\":\"292-310\"},\"PeriodicalIF\":2.3000,\"publicationDate\":\"2025-03-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Semiconductor Manufacturing\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10908704/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Semiconductor Manufacturing","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10908704/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Capacity Estimation for Semiconductor Wafer Fabrication Facilities via an Optimization Model Based on Flexible Lead Times
In this paper, we consider the problem of production capacity estimation for a semiconductor wafer fabrication facility. Capacity estimation involves determining the maximum achievable throughput of a wafer fabrication facility during a given planning horizon in consideration of both product mix and target cycle time. The wafer fabrication facility (fab) is one of the most complex production systems, consisting of hundreds of process steps for each product as well as thousands of processing machines and re-entrant process flows wherein products must visit the same workcenter multiple times. In this regard, estimating production capacity by modeling the wafer manufacturing process is a challenging problem. To properly capture the dynamics of the process, we propose a flexible-lead-time-based optimization model that considers both the state of work-in-process (WIP) over time and the relationship between WIP levels and lead times. The results of simulation experiments using a real-sized instance demonstrate the advantages of the proposed model over existing alternatives.
期刊介绍:
The IEEE Transactions on Semiconductor Manufacturing addresses the challenging problems of manufacturing complex microelectronic components, especially very large scale integrated circuits (VLSI). Manufacturing these products requires precision micropatterning, precise control of materials properties, ultraclean work environments, and complex interactions of chemical, physical, electrical and mechanical processes.