Chaobiao Lin , Ling Hong , Ding Wu , Na Ren , Kuang Sheng
{"title":"重复 UIS 应力期间 1.2 kV 平面 SiC MOSFET 的阈值电压演变","authors":"Chaobiao Lin , Ling Hong , Ding Wu , Na Ren , Kuang Sheng","doi":"10.1016/j.sse.2025.109125","DOIUrl":null,"url":null,"abstract":"<div><div>In this paper, repetitive unclamped inductive switching (UIS) stressing was conducted on 1.2-kV planar silicon carbide (SiC) MOSFETs. Different off-state gate voltage biases (<em>V<sub>gs-off</sub></em> = 0 V/−5 V/−10 V) were applied. The evolution of on-resistance (<em>R<sub>on</sub></em>) and threshold voltage (<em>V<sub>th</sub></em>) in different conditions has been observed. It was found that <em>R<sub>on</sub></em> was increased and <em>V<sub>th</sub></em> was negatively shifted for −5 V and −10 V <em>V<sub>gs-off</sub></em> conditions. Failure analysis was conducted to investigate the <em>R<sub>on</sub></em> degradation mechanism. Aluminum (Al) melting on chip upper surface occurred during UIS stressing, which was verified by scanned-electron-beam observation. Regarding <em>V<sub>th</sub></em> shift, the repetitive UIS stressing applied on the devices was analyzed as a combination of high-temperature reverse bias (HTRB) stress and high-temperature gate bias (HTGB) stress. To aid the mechanism analysis, TCAD simulations of the UIS avalanche process were conducted. When negative <em>V<sub>gs-off</sub></em> was applied, the channel region entered an accumulated state, and the electric field was directed toward the gate oxide. This facilitated hot hole injection into the gate oxide, leading to a significant increase in positive oxide charge density. As the magnitude of the negative <em>V<sub>gs-off</sub></em> bias increased, the electric field stress in the gate oxide and hole density in the channel region were aggravated, resulting in a more pronounced <em>V<sub>th</sub></em> shift.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"227 ","pages":"Article 109125"},"PeriodicalIF":1.4000,"publicationDate":"2025-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Evolution of threshold voltage in 1.2-kV planar SiC MOSFETs during repetitive UIS stressing\",\"authors\":\"Chaobiao Lin , Ling Hong , Ding Wu , Na Ren , Kuang Sheng\",\"doi\":\"10.1016/j.sse.2025.109125\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>In this paper, repetitive unclamped inductive switching (UIS) stressing was conducted on 1.2-kV planar silicon carbide (SiC) MOSFETs. Different off-state gate voltage biases (<em>V<sub>gs-off</sub></em> = 0 V/−5 V/−10 V) were applied. The evolution of on-resistance (<em>R<sub>on</sub></em>) and threshold voltage (<em>V<sub>th</sub></em>) in different conditions has been observed. It was found that <em>R<sub>on</sub></em> was increased and <em>V<sub>th</sub></em> was negatively shifted for −5 V and −10 V <em>V<sub>gs-off</sub></em> conditions. Failure analysis was conducted to investigate the <em>R<sub>on</sub></em> degradation mechanism. Aluminum (Al) melting on chip upper surface occurred during UIS stressing, which was verified by scanned-electron-beam observation. Regarding <em>V<sub>th</sub></em> shift, the repetitive UIS stressing applied on the devices was analyzed as a combination of high-temperature reverse bias (HTRB) stress and high-temperature gate bias (HTGB) stress. To aid the mechanism analysis, TCAD simulations of the UIS avalanche process were conducted. When negative <em>V<sub>gs-off</sub></em> was applied, the channel region entered an accumulated state, and the electric field was directed toward the gate oxide. This facilitated hot hole injection into the gate oxide, leading to a significant increase in positive oxide charge density. As the magnitude of the negative <em>V<sub>gs-off</sub></em> bias increased, the electric field stress in the gate oxide and hole density in the channel region were aggravated, resulting in a more pronounced <em>V<sub>th</sub></em> shift.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"227 \",\"pages\":\"Article 109125\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S003811012500070X\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S003811012500070X","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Evolution of threshold voltage in 1.2-kV planar SiC MOSFETs during repetitive UIS stressing
In this paper, repetitive unclamped inductive switching (UIS) stressing was conducted on 1.2-kV planar silicon carbide (SiC) MOSFETs. Different off-state gate voltage biases (Vgs-off = 0 V/−5 V/−10 V) were applied. The evolution of on-resistance (Ron) and threshold voltage (Vth) in different conditions has been observed. It was found that Ron was increased and Vth was negatively shifted for −5 V and −10 V Vgs-off conditions. Failure analysis was conducted to investigate the Ron degradation mechanism. Aluminum (Al) melting on chip upper surface occurred during UIS stressing, which was verified by scanned-electron-beam observation. Regarding Vth shift, the repetitive UIS stressing applied on the devices was analyzed as a combination of high-temperature reverse bias (HTRB) stress and high-temperature gate bias (HTGB) stress. To aid the mechanism analysis, TCAD simulations of the UIS avalanche process were conducted. When negative Vgs-off was applied, the channel region entered an accumulated state, and the electric field was directed toward the gate oxide. This facilitated hot hole injection into the gate oxide, leading to a significant increase in positive oxide charge density. As the magnitude of the negative Vgs-off bias increased, the electric field stress in the gate oxide and hole density in the channel region were aggravated, resulting in a more pronounced Vth shift.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.