一种用于3.3V I/O应用的pmos嵌入式低压触发可控硅ESD保护装置

IF 1.6 4区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Microelectronics Reliability Pub Date : 2025-03-24 DOI:10.1016/j.microrel.2025.115706

Jun Deng, Hongjiao Yang, Yang Wang, Fengfeng Zhou, Haotian Chen, Beibei Nie, Wei Liu

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引用次数: 0

摘要

本文提出了一种新颖的低触发电压、高鲁棒性静电放电（ESD）保护器件，即pmos嵌入式低压触发可控硅（PLVTSCR），用于0.18 μm CMOS工艺的3.3V I/O保护。第一个改进的PLVTSCR被称为PLVTSCR- a。它是通过在传统的可控硅中引入PMOS来为可控硅提供触发电流，从而降低传统可控硅的触发电压（Vt1），并通过利用PMOS引入额外的寄生可控硅路径进一步增加失效电流（It2）来实现的。第二种改进型PLVTSCR被称为PLVTSCR- b。PLVTSCR-B与PLVTSCR-A的区别在于，PLVTSCR-B没有DNW层，使得寄生NPN的基极区开路，进一步降低了PLVTSCR-A的触发电压。第三种器件称为plvtscc。plvtscc是plvtscc - b的另一种布局结构，它可以在不增加面积的情况下增加器件的保持电流（Ih）和保持电压。该系列器件可显著改善传统可控硅的ESD特性。测量结果表明，与传统可控硅相比，plvtscc的触发电压降低了51.5%，失效电流增加了10.3%。此外，plvtscc的保持电流为328.5 mA，远远高于电路正常工作时的电流，可以有效地防止锁存。此外，新器件有望在深亚微米技术中保护3.3V I/O，并已在0.18 μm CMOS工艺中实现。

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A PMOS-embedded low-voltage triggered silicon controlled rectifier ESD protection device for 3.3V I/O application

In this paper, a novel low-trigger-voltage and high-robustness Electrostatic Discharge (ESD) protection device, called PMOS-embedded Low-Voltage Triggered Silicon Controlled Rectifier (PLVTSCR), is proposed for 3.3V I/O protection application in 0.18 μm CMOS process. The first improved PLVTSCR is called PLVTSCR-A. It is achieved by introducing a PMOS into the traditional SCR to provide a trigger current for SCR, thereby reducing the traditional SCR's trigger voltage (V_t1) and further increasing the failure current (I_t2) by utilizing the PMOS to introduce an additional parasitic SCR path. The second improved PLVTSCR is called PLVTSCR-B. The difference between PLVTSCR-B and PLVTSCR-A is that PLVTSCR-B does not have the DNW layer, making the base region of the parasitic NPN open circuit, further reducing PLVTSCR-A's trigger voltage. The third device is called PLVTSCR-C. PLVTSCR-C is another layout structure of PLVTSCR-B, and it can increase the holding current (I_h) and holding voltage of the device without increasing the area. The proposed series of devices can significantly improve the ESD characteristics of traditional SCR. Measurement results show that the PLVTSCR-C's trigger voltage is reduced by 51.5 %, and the failure current is increased by 10.3 % compared to traditional SCR. Furthermore, the holding current of PLVTSCR-C is 328.5 mA, which is much higher than the current during normal operation of the circuit and can effectively prevent latch-up. Additionally, the new device is expected to protect 3.3V I/O in deep submicron technology and has been implemented in a 0.18 μm CMOS process.

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来源期刊

Microelectronics Reliability 工程技术-工程：电子与电气

CiteScore

3.30

自引率

12.50%

发文量

342

审稿时长

68 days

期刊介绍： Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged. Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.