Asymmetric Trench SiC MOSFET With Integrated Three Channels for Improved Performance and Reliability

A novel Asymmetric Trench SiC MOSFET (ATMOS) with Integrated Three Channels (ITC) is presented, which improves the performance and reliability significantly. The ITC includes the reverse conduction channel (Ch3) and double forward conduction channels (Ch1 and Ch2). The Ch3 is constituted by the Self-Biased MOSFET (SBM), forming a low barrier due to the drain-induced barrier lowering effect, which results in a lower turn on voltage compared with the p-i-n body diode. On the other hand, the Ch1 and Ch2 are constituted by the side trench MOSFET and additional bottom planar MOSFET, respectively. It shortens the width of the JFET region, and a lower gate oxide electric field is achieved. The reverse blocking leakage current (IBL) caused by the drain-induced barrier lowering is suppressed. Moreover, the bottom planar MOSFET reduces the gate-drain charge (QGD) and switching losses due to the reduced coupling area between the Gate and Drain. Finally, The Ch1 and Ch2 provide double electron current paths during forward concoction, which reduces the specific on-resistance (Ron,sp) of the device remarkably. The simulation results show that the proposed ITC-ATMOS achieves a reduction ${\mathrm { V}}_{\mathrm { cut-in}}$ of the body diode from 2.8V to 2.0V at 50A. The peak electric field ${\mathrm { E}}_{\mathrm { max}}$ is reduced to 1.27MV, and the leakage current(IBL) caused by the integrated SBM (I ${_{\text {BL}}} {=} 10{^{-}7 }$ A) is much smaller than integrated Schottky Barrier Diodes (SBD) (I ${_{\text {BL}}} {=} 10{^{-}5 }$ A) for blocking characteristics at high-temperature, thus long-term reliability is greatly enhanced. Moreover, a decrease in ${\mathrm { R}}_{\mathrm { on,sp}}$ of 28.57%, and reductions in ${\mathrm { Q}}_{\mathrm { GD}}$ and switching losses by 20.60% and 41.4% are achieved when compared with the Conventional ATMOS, respectively.