3 纳米以下技术节点上无结 Forksheet FET 的界面陷阱特性分析：数字、模拟/射频和电路应用的可靠性评估

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-12-11 DOI:10.1109/TDMR.2024.3516084

Gowthami Ryali;Bala Subrahmanyam Pitchuka;Venkata Ramakrishna Kotha;Sresta Valasa;Sunitha Bhukya;Praveen Kumar Mudidhe;Shubham Tayal;Bheemudu Vadthya;Hitesh Borkar;Narendar Vadthiya

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引用次数: 0

摘要

最近，由于具有最小n-p间距的FET和FET的无缝集成，Forksheet (FS) FET已经发展成为下一代应用的潜在候选者。然而，困扰设备可靠性的一个严重问题是接口陷阱的存在。因此，在本文中，我们首次分析了亚3nm技术节点中无结（JL） fset的受体和供体界面陷阱电荷（ITCs）的存在，该节点具有用于数字，模拟/RF和电路应用的校准良好的TCAD设置。结果表明，在JL-FSFET器件中，与没有陷阱的情况相比，在fsfet器件中存在受体ITCs和供体ITCs可以提高器件的整体数字性能，开关比为$\sim 10{^{{10}}}$。在较低的VGS下，ITCs的存在显著影响模拟/RF性能，而在一定程度上增加VGS会抑制陷阱效应，导致模拟/RF性能的不变变化，这表明所设计的jl - fset是可靠和鲁棒的。此外，将陷阱浓度从$2\乘以10{^{{12}}}~{\mathrm {cm}}^{-2}$提高到$8\乘以10{^{{12}}}~{\mathrm {cm}}^{-2}$，泄漏电流降低了4个数量级，开关比提高了$ 10{^{{12}}}$，特别是在ffet中存在受体ITCs和供体ITCs的情况下。此外，在较高的VGS下增加陷阱浓度，与没有陷阱时产生相同的模拟/射频性能，使器件即使在较高浓度下也更可靠。设计了jl - fset的CMOS逆变器布局，在有无陷阱的情况下，发现基于陷阱的逆变器与无陷阱的逆变器产生接近相等的增益。总的来说，这项研究为jl - fset在ITCs存在下的可靠性能铺平了道路，这些ITCs将被应用于下一代数字、模拟/射频IC应用。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Interface Trap Characterization in Junctionless Forksheet FET at Sub-3 nm Technology Node: A Reliability Assessment on Digital, Analog/RF, and Circuit Applications

In the recent times, the Forksheet (FS) FET has evolved as a potential candidature for next generation applications due the seamless integration of nFET and pFET with minimal n-p spacing. However, one of the serious concerns that bothers the reliability of devices is the presence of interface traps. Therefore, in this manuscript, for the first time, we aim to analyse the presence of acceptor and donor interface trap charges (ITCs) in sub - 3nm technology node for the Junctionless (JL) FSFET with well calibrated TCAD setup for digital, analog/RF, and circuit applications. Results demonstrated that the presence of acceptor ITCs in nFET and donor ITCs in pFET in the JL-FSFET device improves the overall digital performance of the device with switching ratio

$\sim 10{^{{10}}}$

when compared to no trap scenario. At lower VGS, the presence of ITCs significantly impacted the analog/RF performance whereas increasing the VGS after a certain point overpowered the trap effects producing invariant changes in analog/RF performance indicating that the designed JL-FSFET is reliable and robust. Further, increasing the trap concentration from

$2\times 10{^{{12}}}~{\mathrm { cm}}^{-2}$

$8\times 10{^{{12}}}~{\mathrm { cm}}^{-2}$

reduced the leakage currents in four orders and improved the switching ratio by

$\sim 10{^{{12}}}$

especially with the presence of acceptor ITCs in nFET and donor ITCs in pFET. Moreover, increasing the trap concentration at higher VGS, produced equal analog/RF performance with that of absence of traps making the device more reliable even with higher concentrations. The CMOS inverter layout for the JL-FSFET is designed with the presence and absence of ITCs and found that the ITCs based inverter produces near equal gain to that of no traps. Overall, this research paves a way towards the reliable performance of JL-FSFET in the presence of ITCs to be adopted into next generation digital, analog/RF IC applications.

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来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.