利用纳秒绿色激光退火技术有选择地增大接触/Via 塞的晶粒尺寸

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Jaejoong Jeong , Youngkeun Park , Hwanuk Guim , Yongku Baek , Heetae Kim , Dongbin Kim , Hui Jae Cho , Su-hyeon Gwon , Min Ju Kim , Byung Jin Cho
{"title":"利用纳秒绿色激光退火技术有选择地增大接触/Via 塞的晶粒尺寸","authors":"Jaejoong Jeong ,&nbsp;Youngkeun Park ,&nbsp;Hwanuk Guim ,&nbsp;Yongku Baek ,&nbsp;Heetae Kim ,&nbsp;Dongbin Kim ,&nbsp;Hui Jae Cho ,&nbsp;Su-hyeon Gwon ,&nbsp;Min Ju Kim ,&nbsp;Byung Jin Cho","doi":"10.1016/j.sse.2025.109098","DOIUrl":null,"url":null,"abstract":"<div><div>The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm<sup>2</sup>). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"226 ","pages":"Article 109098"},"PeriodicalIF":1.4000,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing\",\"authors\":\"Jaejoong Jeong ,&nbsp;Youngkeun Park ,&nbsp;Hwanuk Guim ,&nbsp;Yongku Baek ,&nbsp;Heetae Kim ,&nbsp;Dongbin Kim ,&nbsp;Hui Jae Cho ,&nbsp;Su-hyeon Gwon ,&nbsp;Min Ju Kim ,&nbsp;Byung Jin Cho\",\"doi\":\"10.1016/j.sse.2025.109098\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm<sup>2</sup>). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"226 \",\"pages\":\"Article 109098\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-03-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0038110125000437\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125000437","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

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Selective grain size enlargement in Contact/Via plugs using Nanosecond green laser annealing
The rapid decrease in interconnect Critical Dimensions (CDs) within logic devices and growth in the contact height of 3D memory devices have led to increased contact/via plugs resistance. In this study, we introduce an approach to reduce the resistance of the contact/via plugs by engineering the grain size of the plugs using Nanosecond Green Laser Annealing (NGLA) with a low energy fluence (= 0.1 J/cm2). Because of the proximity between adjacent W plugs, diffraction of the laser light can occur which will help the laser energy to be absorbed by the sidewall of the W plugs. In addition, the difference in reflectivity between the plug region and W interconnect lines can cause grain size enlargement to selectively occur in the plug region. The NGLA process increased grain size in the plugs up to 79.9 %, resulting as much as a 26 % reduction in tungsten plug resistance. The standard deviation of the plug resistance was also improved from 14.6 % to 7.9 % after the NGLA process.
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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