M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano
{"title":"2DEG密度和漏源场极板设计对650 V AlGaN/GaN hemt动态ron的影响","authors":"M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano","doi":"10.1016/j.microrel.2025.115666","DOIUrl":null,"url":null,"abstract":"<div><div>The effect of 2DEG density and Drain/Source Field Plate design on dynamic-R<sub>ON</sub> of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static V<sub>DS</sub> stress and Pulsed I-V characterization. C<img>V measurements allowed the extraction of 2DEG density, while Static V<sub>DS</sub> stress and Pulsed I-V put in evidence the partial recovery of the dynamic-R<sub>ON</sub> at high V<sub>DS,stress</sub>, potentially explained by a field-driven hole generation mechanism that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce R<sub>ON</sub>-degradation at high voltages, due to an easier holes generation. Furthermore, Pulsed I-V tests under resistive load switching mode have been addressed, highlighting the impact of the distance between source field plate and drain field plate on the dynamic-R<sub>ON</sub> degradation in conventional switch mode operations.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"168 ","pages":"Article 115666"},"PeriodicalIF":1.6000,"publicationDate":"2025-03-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V AlGaN/GaN HEMTs\",\"authors\":\"M. Cioni , G. Giorgino , A. Chini , N. Zagni , G. Cappellini , S. Principato , C. Miccoli , T. Wakrim , M.E. Castagna , A. Constant , F. Iucolano\",\"doi\":\"10.1016/j.microrel.2025.115666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>The effect of 2DEG density and Drain/Source Field Plate design on dynamic-R<sub>ON</sub> of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static V<sub>DS</sub> stress and Pulsed I-V characterization. C<img>V measurements allowed the extraction of 2DEG density, while Static V<sub>DS</sub> stress and Pulsed I-V put in evidence the partial recovery of the dynamic-R<sub>ON</sub> at high V<sub>DS,stress</sub>, potentially explained by a field-driven hole generation mechanism that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce R<sub>ON</sub>-degradation at high voltages, due to an easier holes generation. Furthermore, Pulsed I-V tests under resistive load switching mode have been addressed, highlighting the impact of the distance between source field plate and drain field plate on the dynamic-R<sub>ON</sub> degradation in conventional switch mode operations.</div></div>\",\"PeriodicalId\":51131,\"journal\":{\"name\":\"Microelectronics Reliability\",\"volume\":\"168 \",\"pages\":\"Article 115666\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2025-03-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0026271425000794\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271425000794","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
摘要
本文研究了2DEG密度和漏源场极板设计对650 V p-GaN栅极AlGaN/GaN hemt动态ron的影响。通过电容电压测量、静态VDS应力和脉冲I-V表征,对具有三种不同AlGaN势垒和p-GaN层设计的器件进行了测试。CV测量可以提取2DEG密度,而静态VDS应力和脉冲I-V则证明了在高VDS应力下动态ron的部分恢复,这可能是由场驱动的空穴产生机制部分补偿了GaN缓冲液中的负电离碳受体。这一假设与在不同2DEG密度和不同漏极场板设计下观察到的趋势一致,表明在高电压下,由于更容易产生空穴,在漏极下较高的电场可以显著降低ron退化。此外,还讨论了电阻负载切换模式下的脉冲I-V试验,强调了传统切换模式下源场板和漏场板之间的距离对动态ron退化的影响。
Effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V AlGaN/GaN HEMTs
The effect of 2DEG density and Drain/Source Field Plate design on dynamic-RON of 650 V p-GaN gate AlGaN/GaN HEMTs is investigated in this work. Devices presenting three different AlGaN barrier and p-GaN layer design have been tested by means of Capacitance-Voltage measurements, Static VDS stress and Pulsed I-V characterization. CV measurements allowed the extraction of 2DEG density, while Static VDS stress and Pulsed I-V put in evidence the partial recovery of the dynamic-RON at high VDS,stress, potentially explained by a field-driven hole generation mechanism that partially compensates negatively ionized Carbon acceptors in the GaN Buffer. This hypothesis is in line with the trends observed for different 2DEG density and different drain field-plate designs, suggesting that a higher electric field under the drain terminal can significantly reduce RON-degradation at high voltages, due to an easier holes generation. Furthermore, Pulsed I-V tests under resistive load switching mode have been addressed, highlighting the impact of the distance between source field plate and drain field plate on the dynamic-RON degradation in conventional switch mode operations.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.