Effect of gate oxide thickness on gate latent damage induced by heavy ion in SiC power MOSFETs

SiC materials and devices hold significant promise for aerospace applications owing to their high thermal conductivity, temperature tolerance, and resistance to harsh conditions. However, SiC power devices often encounter single event effects (SEEs) induced by high-energy ions, which limit the applications in space radiation environments. In this study, we demonstrate the impact of thickness of gate oxide layer on latent gate oxide damage in Silicon carbide (SiC) power metal oxide semiconductor field effect transistors (MOSFETs) during heavy-ion irradiation, by using a combination of experiments and technical computer-aided design (TCAD) simulations. The study exposes SiC MOSFETs with gate oxide thicknesses of 40 nm and 60 nm to 78Kr ion irradiation followed by post-irradiation gate stress (PIGS) tests, scrutinizing failure characteristics induced by irradiation. Through TCAD simulations, the internal dynamics of the gate oxide layer are scrutinized, revealing that escalated electric fields and localized energy pulses predominantly precipitate gate dielectric layer damage. The results suggest that gate oxide thickness markedly impacts latent gate damage, with thinner oxide layers exhibiting heightened susceptibility to electrical breakdown. These findings enrich the comprehension of SiC power device reliability in radiation-rich environments, furnishing invaluable insights for aerospace applications.