工作在正向和反向模式下的V-FET的模拟行为

IF 1.4 4区物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

Solid-state Electronics Pub Date : 2025-01-22 DOI:10.1016/j.sse.2025.109073

V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian

{"title":"工作在正向和反向模式下的V-FET的模拟行为","authors":"V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian","doi":"10.1016/j.sse.2025.109073","DOIUrl":null,"url":null,"abstract":"<div><div>This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (AV) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, VEA and AV, in the reverse mode shows better gmsat, SSsat and fT. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (fT) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, AV = 28 dB and fT = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and fT = 3.7 GHz in reverse mode.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109073"},"PeriodicalIF":1.4000,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analog behavior of V-FET operating in forward and reverse mode\",\"authors\":\"V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian\",\"doi\":\"10.1016/j.sse.2025.109073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (AV) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, VEA and AV, in the reverse mode shows better gmsat, SSsat and fT. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (fT) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, AV = 28 dB and fT = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and fT = 3.7 GHz in reverse mode.</div></div>\",\"PeriodicalId\":21909,\"journal\":{\"name\":\"Solid-state Electronics\",\"volume\":\"225 \",\"pages\":\"Article 109073\"},\"PeriodicalIF\":1.4000,\"publicationDate\":\"2025-01-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Solid-state Electronics\",\"FirstCategoryId\":\"101\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0038110125000188\",\"RegionNum\":4,\"RegionCategory\":\"物理与天体物理\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125000188","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本文研究了基于绝缘体上硅（SOI）晶圆的p型垂直场效应纳米线晶体管（v - fet）的模拟参数，重点研究了沟道（纳米线）直径（CD）的变化以及两种不同的工作模式：正向（源作为底部电极）和反向（源作为顶部电极）。当正向模式下CD从40 nm减小到20 nm时，亚阈值摆幅（SS）从93 mV/dec提高到76 mV/dec，漏极诱导势垒降低（DIBL）从138 mV/V提高到43 mV/V，本征电压增益（AV）从19 dB增加到34 dB。CD的减小增强了通道上栅极的静电控制，从而改善了晶体管的特性。在正向模式下，观察到顶部电极的接入电阻的显著影响。正向模式下的DIBL、VEA和AV均有改善，而反向模式下的gmsat、SSsat和fT均有改善。此外，通过对逆变系数(IC) = 63, AV = 28 dB, fT = 2.6 GHz，以及反向模式下IC = 34, AV = 20 dB, fT = 3.7 GHz时，固有电压增益和单位增益频率（fT）之间的权衡分析，得出强版本的最优点。

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Analog behavior of V-FET operating in forward and reverse mode

This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (A_V) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, V_EA and A_V, in the reverse mode shows better gm_sat, SS_sat and f_T. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (f_T) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, A_V = 28 dB and f_T = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and f_T = 3.7 GHz in reverse mode.

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来源期刊

Solid-state Electronics 物理-工程：电子与电气

CiteScore

3.00

自引率

5.90%

发文量

212

审稿时长

3 months

期刊介绍： It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.