z向组件(ZDC)在电源完整性中的系统级应用

Pranay Vuppunutala;Xiaolu Zhu;Junyong Park;Keith B. Hardin;Zachary C. N. Kratzer;John T. Fessler;Biyao Zhao;Siqi Bai
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摘要

配电网络(PDN)的设计涉及在集成电路(ic)周围精心放置几个去耦电容器,以减轻开关固有的噪声。一种新技术电容器,z向元件(ZDC),可以通过PCB瞄准IC封装球上的印刷电路板(PCB)元件位置。采用传统表面贴装技术(SMT)去耦解决方案的市售PCB PDN设计,利用市售仿真工具进行了分析,并通过阻抗测量进行了验证。通过将ZDC电容模型代入SMT电容,预测了系统中ZDC PDN的性能。验证是使用PCB上的双端口PDN测量进行的。最后,利用空腔模型和平面对部分单元等效电路技术建立了等效电路模型,以表示与从所有去耦电容器到集成电路的电流路径相关的物理特性。商业工具的仿真结果与测量和等效电路模型都得到了证实。结果表明,与此设计的SMT解决方案相比,选择ZDC作为去耦解决方案可以提供显着降低的阻抗。因此,对于未来的电源完整性应用,ZDC方法是一种很有前途的解耦解决方案,增强了系统的电源完整性性能,与采用SMT策略相比,有助于使用具有成本效益的低层计数pcb,实现更高的速度。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
System-Level Application of the Z-Directed Component (ZDC) for Power Integrity
The design of the power distribution network (PDN) involves the careful placement of several decoupling capacitors around the integrated circuits (ICs) to mitigate the noise inherent with switching. A new technology capacitor, Z-directed component (ZDC), can target printed circuit board (PCB) component locations at the package balls of the IC through the PCB. A commercially available PCB PDN design, using a conventional surface mount technology (SMT) decoupling solution, was analyzed utilizing a commercially available simulation-based tool and validated by impedance measurements. The ZDC PDN performance in the system was predicted by substituting a ZDC capacitor model for selected SMT capacitors. The validation was carried out using two-port PDN measurements on the PCB. Finally, an equivalent circuit model is developed using cavity model and plane-pair partial element equivalent circuit techniques to represent the physics associated with current paths from all the decoupling capacitors to the IC. The simulation results from a commercial tool are corroborated with both the measurements and an equivalent circuit model. It is demonstrated that opting for ZDC as a decoupling solution can deliver significantly lower impedances as compared to the SMT solution for this design. Thus, the ZDC approach is a promising decoupling solution for future power integrity applications, enhancing the power integrity performance of the system, facilitating the use of cost-effective lower layer count PCBs for much higher speeds than adopting an SMT strategy.
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