圆柱形垂直双环绕栅a-InGaZnO场效应管的TCAD仿真研究及几何参数优化

IF 2.4 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Journal of the Electron Devices Society Pub Date : 2025-01-10 DOI:10.1109/JEDS.2025.3528073

Yue Zhao;Lihua Xu;Chuanke Chen;Xufan Li;Kexin Shang;Di Geng;Lingfei Wang;Ling Li

{"title":"圆柱形垂直双环绕栅a-InGaZnO场效应管的TCAD仿真研究及几何参数优化","authors":"Yue Zhao;Lihua Xu;Chuanke Chen;Xufan Li;Kexin Shang;Di Geng;Lingfei Wang;Ling Li","doi":"10.1109/JEDS.2025.3528073","DOIUrl":null,"url":null,"abstract":"Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of <inline-formula> <tex-math>$G_{2}$ </tex-math></inline-formula> significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":"13 ","pages":"66-72"},"PeriodicalIF":2.4000,"publicationDate":"2025-01-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10836807","citationCount":"0","resultStr":"{\"title\":\"TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization\",\"authors\":\"Yue Zhao;Lihua Xu;Chuanke Chen;Xufan Li;Kexin Shang;Di Geng;Lingfei Wang;Ling Li\",\"doi\":\"10.1109/JEDS.2025.3528073\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of <inline-formula> <tex-math>$G_{2}$ </tex-math></inline-formula> significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.\",\"PeriodicalId\":13210,\"journal\":{\"name\":\"IEEE Journal of the Electron Devices Society\",\"volume\":\"13 \",\"pages\":\"66-72\"},\"PeriodicalIF\":2.4000,\"publicationDate\":\"2025-01-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10836807\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of the Electron Devices Society\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10836807/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10836807/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

非晶In-Ga-Zn-O场效应晶体管（a- igzo FET）的阈值控制通常是通过调整材料成分来实现的关键问题。相反，这项工作报告了一个圆柱形垂直双包围栅极（DSG） a- igzo场效应管，具有阈值调制的灵活性，通过三维技术计算机辅助设计（TCAD）模拟。首先，对单门垂直晶体管实验的物理参数进行了校准。然后，通过在各种外门电压（G2）下扫描内门（G1）偏置电压来模拟性能，表明阈值调制的能力。$G_{2}$的长度缩放和位置变化显著影响晶体管性能指标。为了深入理解尺寸依赖性，考虑空间和几何效应，系统地研究了超薄外栅电极的沟道表面电位和电极附近的电场分布。这些结果将推动未来基于dsg -a- igzo - fet的超大尺寸高密度M3D存储器的设计技术协同优化流程。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

TCAD Simulation Study of Cylindrical Vertical Double-Surrounding-Gate a-InGaZnO FETs and Geometric Parameter Optimization

Threshold control of amorphous In-Ga-Zn-O field-effect transistor (a-IGZO FET) is generally a critical issue through material composition adjustment. Instead, this work reports a cylindrical vertical double-surrounding-gate (DSG) a-IGZO FET, featuring flexibility of threshold modulation, by the 3-D technology computer-aided design (TCAD) simulation. Firstly, physics-based parameters are calibrated to single-gated vertical transistor experiments. Thereafter, the performance is simulated by sweeping inner gate (G1) bias voltages under the various outer gate (G2) voltages, indicating the ability of threshold modulation. Length-scaling and position-variation of

$G_{2}$

significantly impact the transistor performance metrics. For in-depth understanding of dimensional dependence, the surface potential of the channel and the electric field distribution near electrode are systematically investigated for an ultra-thin outer gate electrode, via considering spatial and geometric effects. These results will boost a design technology co-optimization flow of the future DSG-a-IGZO-FET-based extremely large-scale and high-density M3D memory.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology

CiteScore

5.20

自引率

4.30%

发文量

124

审稿时长

9 weeks

期刊介绍： The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.