极高栅极电压应力下SiC mosfet栅氧化可靠性评估

IF 2.5 3区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Device and Materials Reliability Pub Date : 2024-10-18 DOI:10.1109/TDMR.2024.3478220

Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang

{"title":"极高栅极电压应力下SiC mosfet栅氧化可靠性评估","authors":"Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang","doi":"10.1109/TDMR.2024.3478220","DOIUrl":null,"url":null,"abstract":"This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage \n<inline-formula> <tex-math>$(V_{T})$ </tex-math></inline-formula>\n shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.","PeriodicalId":448,"journal":{"name":"IEEE Transactions on Device and Materials Reliability","volume":"24 4","pages":"631-636"},"PeriodicalIF":2.5000,"publicationDate":"2024-10-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress\",\"authors\":\"Jianbin Guo;Zhehong Qian;Hang Xu;Bangmin Zhu;Yafen Yang;David Wei Zhang\",\"doi\":\"10.1109/TDMR.2024.3478220\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage \\n<inline-formula> <tex-math>$(V_{T})$ </tex-math></inline-formula>\\n shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.\",\"PeriodicalId\":448,\"journal\":{\"name\":\"IEEE Transactions on Device and Materials Reliability\",\"volume\":\"24 4\",\"pages\":\"631-636\"},\"PeriodicalIF\":2.5000,\"publicationDate\":\"2024-10-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Device and Materials Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10723265/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Device and Materials Reliability","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10723265/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本研究旨在评估碳化硅（SiC）金属氧化物半导体场效应晶体管（MOSFET）在极高栅极电压应力下的可靠性。研究结果表明，SiCMOS对极高栅极电压应力具有一定的鲁棒性。高正偏压（PBS）和高负偏压（NBS）后，室温下的降解主要是由注孔引起的。在高温下，界面态陷阱的增加似乎在PBS下的降解中起重要作用。用C-V特性和应力后器件的恢复来解释退化。在高PBS条件下，降解可能是可恢复的。恢复后，阈值电压$(V_{T})$ shift小于0.1V。而高NBS下的损害是永久性的，不可恢复的。值得注意的是，测试设备在极高栅极电压应力下的稳健性也得到了验证，特别是极端PBS。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Evaluations of Gate Oxide Reliability in SiC MOSFETs Under Extremely High Gate Voltage Stress

This study aimed to evaluate the reliability of Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) under extremely high gate voltage stress. The research results show that SiCMOS has certain robustness to extremely high gate voltage stress. After high positive bias stress (PBS) and high negative bias stress (NBS), degradation at room temperature is mainly caused by the injection of holes. At high temperatures, the increased interface state traps appear to play an important role in the degradation under PBS. Both C-V characteristics and the recovery of devices after stress are used to explain the degradation. Degradation under high PBS might be recoverable. After recovery, the threshold voltage

$(V_{T})$

shift is less than 0.1V. Whereas damage under high NBS is permanent and unrecoverable. Remarkably, the robustness of the device under test to extremely high gate voltage stress is also verified, especially extreme PBS.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE Transactions on Device and Materials Reliability 工程技术-工程：电子与电气

CiteScore

4.80

自引率

5.00%

发文量

审稿时长

6-12 weeks

期刊介绍： The scope of the publication includes, but is not limited to Reliability of: Devices, Materials, Processes, Interfaces, Integrated Microsystems (including MEMS & Sensors), Transistors, Technology (CMOS, BiCMOS, etc.), Integrated Circuits (IC, SSI, MSI, LSI, ULSI, ELSI, etc.), Thin Film Transistor Applications. The measurement and understanding of the reliability of such entities at each phase, from the concept stage through research and development and into manufacturing scale-up, provides the overall database on the reliability of the devices, materials, processes, package and other necessities for the successful introduction of a product to market. This reliability database is the foundation for a quality product, which meets customer expectation. A product so developed has high reliability. High quality will be achieved because product weaknesses will have been found (root cause analysis) and designed out of the final product. This process of ever increasing reliability and quality will result in a superior product. In the end, reliability and quality are not one thing; but in a sense everything, which can be or has to be done to guarantee that the product successfully performs in the field under customer conditions. Our goal is to capture these advances. An additional objective is to focus cross fertilized communication in the state of the art of reliability of electronic materials and devices and provide fundamental understanding of basic phenomena that affect reliability. In addition, the publication is a forum for interdisciplinary studies on reliability. An overall goal is to provide leading edge/state of the art information, which is critically relevant to the creation of reliable products.