Luigi Colombo;Salim El Kazzi;Mihaela Popovici;Gilles Delie;Dae Seon Kwon;Sean RC McMitchell;Christoph Adelmann
{"title":"超硅集成电路的未来材料展望","authors":"Luigi Colombo;Salim El Kazzi;Mihaela Popovici;Gilles Delie;Dae Seon Kwon;Sean RC McMitchell;Christoph Adelmann","doi":"10.1109/TMAT.2024.3497835","DOIUrl":null,"url":null,"abstract":"The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopted in recent decades to enhance the performance of Si integrated circuits. The imperative to uphold Moore's Law for both More Moore and More than Moore devices has driven the industry to study, and later introduce a plethora of materials and innovative processes into the Si fabrication process, spanning from the front-end-of-line (FEOL) to the back-end-of-line (BEOL). This concerted effort aims to bolster computing power and functionality while curbing costs. Scaling Si-channel transistors down to the nanometer level has presented formidable challenges. The emergence of new materials, such as two-dimensional materials like transition metal dichalcogenides, carbon nanotubes, and metal oxides holds promise for further scaling endeavors. With transistors and interconnects nearing their physical limits, these materials offer potential solutions by enabling the fabrication of high-performance devices without relying solely on Si, while integrated at lower thermal budgets. Moreover, these technologies can be repurposed in the BEOL to add extra functionality while reducing the overall device footprint. Recent breakthroughs, notably the successful demonstration of high-performance devices utilizing ALD metal oxides like In\n<sub>2</sub>\nO\n<sub>3</sub>\n, have sparked considerable excitement. Addressing the scaling challenges of interconnects is equally daunting. The quest for materials with lower resistivities than copper interconnects with reduced electromigration at scaled dimensions and efforts to eliminate or minimize barrier layers hold promise in mitigating RC time delay. Non-volatile memories, particularly ferroelectric-based memories, stand to be gained from advancements in materials science. Innovations in such materials as hafnates and enhanced integration techniques for perovskites through electrode stack engineering could facilitate the scaling of current ferroelectric memories. The ongoing introduction of new materials is poised to sustain scaling efforts and unlock novel functionalities in electronic devices for many years.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"178-193"},"PeriodicalIF":0.0000,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Future Materials for Beyond Si Integrated Circuits: A Perspective\",\"authors\":\"Luigi Colombo;Salim El Kazzi;Mihaela Popovici;Gilles Delie;Dae Seon Kwon;Sean RC McMitchell;Christoph Adelmann\",\"doi\":\"10.1109/TMAT.2024.3497835\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopted in recent decades to enhance the performance of Si integrated circuits. The imperative to uphold Moore's Law for both More Moore and More than Moore devices has driven the industry to study, and later introduce a plethora of materials and innovative processes into the Si fabrication process, spanning from the front-end-of-line (FEOL) to the back-end-of-line (BEOL). This concerted effort aims to bolster computing power and functionality while curbing costs. Scaling Si-channel transistors down to the nanometer level has presented formidable challenges. The emergence of new materials, such as two-dimensional materials like transition metal dichalcogenides, carbon nanotubes, and metal oxides holds promise for further scaling endeavors. With transistors and interconnects nearing their physical limits, these materials offer potential solutions by enabling the fabrication of high-performance devices without relying solely on Si, while integrated at lower thermal budgets. Moreover, these technologies can be repurposed in the BEOL to add extra functionality while reducing the overall device footprint. Recent breakthroughs, notably the successful demonstration of high-performance devices utilizing ALD metal oxides like In\\n<sub>2</sub>\\nO\\n<sub>3</sub>\\n, have sparked considerable excitement. Addressing the scaling challenges of interconnects is equally daunting. The quest for materials with lower resistivities than copper interconnects with reduced electromigration at scaled dimensions and efforts to eliminate or minimize barrier layers hold promise in mitigating RC time delay. Non-volatile memories, particularly ferroelectric-based memories, stand to be gained from advancements in materials science. Innovations in such materials as hafnates and enhanced integration techniques for perovskites through electrode stack engineering could facilitate the scaling of current ferroelectric memories. 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引用次数: 0
摘要
自从硅成为晶体管和后来的集成电路的首选材料以来,新材料的集成一直是推进硅基器件的关键。近几十年来,新材料被迅速采用,以提高硅集成电路的性能。对于More Moore和More than Moore器件来说,维护摩尔定律的必要性推动了该行业的研究,并随后在Si制造过程中引入了大量的材料和创新工艺,从前端线(FEOL)到后端线(BEOL)。这种协同的努力旨在增强计算能力和功能,同时控制成本。将硅沟道晶体管缩小到纳米级是一个艰巨的挑战。新材料的出现,如过渡金属二硫族化合物、碳纳米管和金属氧化物等二维材料,为进一步扩大规模带来了希望。随着晶体管和互连接近其物理极限,这些材料提供了潜在的解决方案,使制造高性能器件无需完全依赖于Si,同时集成在更低的热预算。此外,这些技术可以在BEOL中重新利用,以增加额外的功能,同时减少整体设备占用空间。最近的突破,特别是利用ALD金属氧化物(如In2O3)的高性能器件的成功演示,引发了相当大的兴奋。解决互连的规模挑战同样令人生畏。寻求比铜互连具有更低电阻率的材料,在缩放尺寸上减少电迁移,并努力消除或最小化屏障层,有望减轻RC时间延迟。非易失性存储器,特别是基于铁电的存储器,将从材料科学的进步中获得。诸如铪酸盐等材料的创新和通过电极堆叠工程增强的钙钛矿集成技术可以促进当前铁电存储器的缩放。正在进行的新材料的引入准备维持规模的努力,并解锁多年的电子设备的新功能。
Future Materials for Beyond Si Integrated Circuits: A Perspective
The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopted in recent decades to enhance the performance of Si integrated circuits. The imperative to uphold Moore's Law for both More Moore and More than Moore devices has driven the industry to study, and later introduce a plethora of materials and innovative processes into the Si fabrication process, spanning from the front-end-of-line (FEOL) to the back-end-of-line (BEOL). This concerted effort aims to bolster computing power and functionality while curbing costs. Scaling Si-channel transistors down to the nanometer level has presented formidable challenges. The emergence of new materials, such as two-dimensional materials like transition metal dichalcogenides, carbon nanotubes, and metal oxides holds promise for further scaling endeavors. With transistors and interconnects nearing their physical limits, these materials offer potential solutions by enabling the fabrication of high-performance devices without relying solely on Si, while integrated at lower thermal budgets. Moreover, these technologies can be repurposed in the BEOL to add extra functionality while reducing the overall device footprint. Recent breakthroughs, notably the successful demonstration of high-performance devices utilizing ALD metal oxides like In
2
O
3
, have sparked considerable excitement. Addressing the scaling challenges of interconnects is equally daunting. The quest for materials with lower resistivities than copper interconnects with reduced electromigration at scaled dimensions and efforts to eliminate or minimize barrier layers hold promise in mitigating RC time delay. Non-volatile memories, particularly ferroelectric-based memories, stand to be gained from advancements in materials science. Innovations in such materials as hafnates and enhanced integration techniques for perovskites through electrode stack engineering could facilitate the scaling of current ferroelectric memories. The ongoing introduction of new materials is poised to sustain scaling efforts and unlock novel functionalities in electronic devices for many years.