基于 AlScN 的铁电隧道结的计算研究

IF 1.4 4区 物理与天体物理 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Ning Yang, Guoting Cheng, Jing Guo
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引用次数: 0

摘要

铁电(FE)AlScN 材料已在存储器和神经形态计算设备应用方面进行了实验探索。在此,我们进行了一项计算研究,以模拟基于 AlScN 的铁电隧道结 (FTJ) 的器件特性并评估其性能潜力。我们根据原子序数密度泛函理论计算得出的 AlScN 复杂能带结构,为高效的 k⋅p 哈密顿参数设置了参数,从而实现了 FTJ 器件的高效量子输运模拟。与金属-FE-半导体 FTJ 器件结构相比,金属-FE-石墨烯结构增强了势垒高度调制和隧穿电阻(TER)比。在 25 μC/cm2 的 FE 极化条件下,导通态和关断态之间的势垒高度调制可达 0.7eV。减小 AlScN 隧道层厚度对于增加器件导通电流和减少读取延迟非常重要。这些结果表明了接触设计和 FE 层厚度在基于 AlScN 的 FTJ 器件设计中的重要性,并凸显了 AlScN FTJ 在未来存储器件技术应用中的潜力。
本文章由计算机程序翻译,如有差异,请以英文原文为准。

A computational study of AlScN-based ferroelectric tunnel junction

A computational study of AlScN-based ferroelectric tunnel junction
Ferroelectric (FE) AlScN materials have been experimentally explored for memory and neuromorphic computing device applications. Here a computational study is performed to simulate the device characteristics and assess the performance potential of a ferroelectric tunnel junction (FTJ) based on AlScN. We parameterize an efficient kp Hamiltonian from the complex band structure of AlScN from ab initio density-functional theory calculations to enable efficient quantum transport simulations of the FTJ device. Using a metal–FE–graphene structure enhances the barrier height modulation and the tunneling electroresistance (TER) ratio, compared to a metal–FE–semiconductor FTJ device structure. The barrier height modulation between ON and OFF states can reach 0.7eV with a FE polarization of 25 μC/cm2. Reducing the AlScN tunnel layer thickness is important for increasing the device ON current and reducing the read latency. The results indicate the importance of contact designs and FE layer thickness in the design of AlScN-based FTJ devices, and highlight the potential of AlScN FTJ for future memory device technology applications.
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来源期刊
Solid-state Electronics
Solid-state Electronics 物理-工程:电子与电气
CiteScore
3.00
自引率
5.90%
发文量
212
审稿时长
3 months
期刊介绍: It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.
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