{"title":"通过先进的金属层技术优化无掺杂 TFET 性能的可靠性","authors":"Bandi Venkata Chandan, Madhura Prashant Bakshi, Kaushal Kumar Nigam","doi":"10.1016/j.microrel.2024.115542","DOIUrl":null,"url":null,"abstract":"<div><div>To address the low ON-current and reliability issues of dopant-free TFETs, we have incorporated a metal-layer near the source/channel (S/C) interface. The use of this metal layer facilitates a larger flow of electrons near the junction, which helps the ON-current (<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span>) exceed 10<sup>−4</sup> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> under lower biasing conditions. This enhancement in <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span> improves various performance metrics in analog, RF, and linearity applications. Furthermore to assess dependability, we analyzed the impact of acceptor and donor charges on the DL-MS-TFET, focusing on trap effects near interface (ITCs). The results reveal that the presence of these trap charges significantly affects the flat-band voltage, leading to reduced variations in the performance of DL-MS-TFETs. Furthermore, we observed the influence of the metal strip work function on DC performance characteristics. A noticeable decrease in ON-current was found as the metal layer work function increased. Overall, the MS-dopant-free TFET demonstrates superior performance in the presence of ITCs, making it suitable for low-voltage and analog-RF applications.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"163 ","pages":"Article 115542"},"PeriodicalIF":1.6000,"publicationDate":"2024-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Reliability optimization of dopant-free TFET performance through advanced metal layer techniques\",\"authors\":\"Bandi Venkata Chandan, Madhura Prashant Bakshi, Kaushal Kumar Nigam\",\"doi\":\"10.1016/j.microrel.2024.115542\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>To address the low ON-current and reliability issues of dopant-free TFETs, we have incorporated a metal-layer near the source/channel (S/C) interface. The use of this metal layer facilitates a larger flow of electrons near the junction, which helps the ON-current (<span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span>) exceed 10<sup>−4</sup> A/<span><math><mrow><mi>μ</mi><mi>m</mi></mrow></math></span> under lower biasing conditions. This enhancement in <span><math><msub><mrow><mi>I</mi></mrow><mrow><mi>O</mi><mi>N</mi></mrow></msub></math></span> improves various performance metrics in analog, RF, and linearity applications. Furthermore to assess dependability, we analyzed the impact of acceptor and donor charges on the DL-MS-TFET, focusing on trap effects near interface (ITCs). The results reveal that the presence of these trap charges significantly affects the flat-band voltage, leading to reduced variations in the performance of DL-MS-TFETs. Furthermore, we observed the influence of the metal strip work function on DC performance characteristics. A noticeable decrease in ON-current was found as the metal layer work function increased. Overall, the MS-dopant-free TFET demonstrates superior performance in the presence of ITCs, making it suitable for low-voltage and analog-RF applications.</div></div>\",\"PeriodicalId\":51131,\"journal\":{\"name\":\"Microelectronics Reliability\",\"volume\":\"163 \",\"pages\":\"Article 115542\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2024-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0026271424002221\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424002221","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Reliability optimization of dopant-free TFET performance through advanced metal layer techniques
To address the low ON-current and reliability issues of dopant-free TFETs, we have incorporated a metal-layer near the source/channel (S/C) interface. The use of this metal layer facilitates a larger flow of electrons near the junction, which helps the ON-current () exceed 10−4 A/ under lower biasing conditions. This enhancement in improves various performance metrics in analog, RF, and linearity applications. Furthermore to assess dependability, we analyzed the impact of acceptor and donor charges on the DL-MS-TFET, focusing on trap effects near interface (ITCs). The results reveal that the presence of these trap charges significantly affects the flat-band voltage, leading to reduced variations in the performance of DL-MS-TFETs. Furthermore, we observed the influence of the metal strip work function on DC performance characteristics. A noticeable decrease in ON-current was found as the metal layer work function increased. Overall, the MS-dopant-free TFET demonstrates superior performance in the presence of ITCs, making it suitable for low-voltage and analog-RF applications.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.