基于数字 SRAM 的计算内存宏，支持并行维护网络管理

IF 2.2 Q3 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE

IEEE Solid-State Circuits Letters Pub Date : 2024-10-10 DOI:10.1109/LSSC.2024.3477619

Geng Li;Hanqing Zheng;Jiacong Sun;Hailong Jiao

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引用次数: 0

摘要

为实现网络管理中统计计数器的并行维护，提出了一种基于数字 SRAM 的内存计算（CIM）宏。设计了一种新的 18 晶体管位元组，以支持原位计数器维护。利用联合编码方案和菊花链电路提高了吞吐量，并减少了计算能耗和面积。与采用 55 纳米 CMOS 技术的传统统计计数器相比，所提出的 CIM 宏在 1.2 V 电压下可节省 6.9 美元的能耗和 2.33 美元的面积。

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A Digital SRAM-Based Computing-in-Memory Macro Supporting Parallel Maintaining for Network Management

A digital SRAM-based computing-in-memory (CIM) macro is proposed to enable parallel maintaining for statistics counters in network management. A new 18-transistor bit-cell is designed to support in-situ counter maintaining. A joint coding scheme and a daisy-chain circuit are leveraged to enhance the throughput as well as reduce the computing energy consumption and area. The proposed CIM macro saves

$6.9\times $

in energy at 1.2 V and

$2.33\times $

in area compared with the conventional statistics counters in a 55-nm CMOS technology.

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来源期刊

IEEE Solid-State Circuits Letters Engineering-Electrical and Electronic Engineering

CiteScore

4.30

自引率

3.70%

发文量