Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai
{"title":"具有阶跃源极和优化 LOCOS 结构的 SEGR 加硬沟道栅 DMOS","authors":"Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai","doi":"10.1016/j.microrel.2024.115525","DOIUrl":null,"url":null,"abstract":"<div><div>When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.</div></div>","PeriodicalId":51131,"journal":{"name":"Microelectronics Reliability","volume":"162 ","pages":"Article 115525"},"PeriodicalIF":1.6000,"publicationDate":"2024-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A SEGR hardened trench gate DMOS with stepped source and optimized LOCOS structure\",\"authors\":\"Yanfei Zhang , Xueqin Gong , Mengxin Liu , Xiaoxia Wen , Xiaowu Cai\",\"doi\":\"10.1016/j.microrel.2024.115525\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"<div><div>When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.</div></div>\",\"PeriodicalId\":51131,\"journal\":{\"name\":\"Microelectronics Reliability\",\"volume\":\"162 \",\"pages\":\"Article 115525\"},\"PeriodicalIF\":1.6000,\"publicationDate\":\"2024-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Microelectronics Reliability\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://www.sciencedirect.com/science/article/pii/S0026271424002051\",\"RegionNum\":4,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Reliability","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0026271424002051","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
A SEGR hardened trench gate DMOS with stepped source and optimized LOCOS structure
When irradiation experiment with heavy ions is carried out, Single-Event Gate Rupture (SEGR) is found for the conventional trench-gate DMOS (TG-DMOS) with LOCOS (Local Oxidation of Silicon). FIB analysis show that the failure spot is at the corner of the trench, which is the weakest point of the trench. In this paper, a SEGR hardened TG-DMOS with stepped source and optimized LOCOS structure is proposed. Stepped source is adopted to obtain a narrow base region and less voltage drop when the minority holes travel through the base region, which alleviates the electric field in the trench corner. Optimized LOCOS structure includes local oxidation area not only at the bottom of the gate trench but also at partial sidewall of the trench near the corner, protecting the trench corner and have no effect on the electrical characteristic. For the proposed structure, simulation shows that the peak electric field in the gate oxide is 3.8 MV/cm, which is almost half of the conventional TG-DMOS, and SEGR performance could be improved effectively.
期刊介绍:
Microelectronics Reliability, is dedicated to disseminating the latest research results and related information on the reliability of microelectronic devices, circuits and systems, from materials, process and manufacturing, to design, testing and operation. The coverage of the journal includes the following topics: measurement, understanding and analysis; evaluation and prediction; modelling and simulation; methodologies and mitigation. Papers which combine reliability with other important areas of microelectronics engineering, such as design, fabrication, integration, testing, and field operation will also be welcome, and practical papers reporting case studies in the field and specific application domains are particularly encouraged.
Most accepted papers will be published as Research Papers, describing significant advances and completed work. Papers reviewing important developing topics of general interest may be accepted for publication as Review Papers. Urgent communications of a more preliminary nature and short reports on completed practical work of current interest may be considered for publication as Research Notes. All contributions are subject to peer review by leading experts in the field.