Understanding Bias Stress-Induced Instabilities in ALD-Deposited ZnO FeFETs Featuring HZO-Al2O3-HZO Ferroelectric Stack

In this work, we investigate the threshold voltage ( ${V}_{\text {TH}}\text {)}$ and memory window (MW) dynamics under positive and negative bias stress (PBS/NBS) in atomic layer deposition (ALD)-grown zinc oxide (ZnO) ferroelectric field-effect transistors (FeFETs). The gate stack is engineered by inserting an Al2O3 layer between Zr-doped HfO2 (HZO) layers to form an HZO-Al2O3-HZO configuration. This enhances the MW of ZnO FeFETs to 1.75 V compared to devices without the Al2O3 insertion. From bias stress characterizations, notable results are obtained, especially under NBS conditions. It is revealed that the generation of disorder state (DS) O $^{{2}-}$ defects plays a key role when devices are stressed by negative bias, leading to an abnormal positive shift in ${V}_{\text {TH}}$ . Importantly, the degradation in MW caused by polarization pinning during NBS is mitigated by applying an even more negative bias. This can be explained by enhanced polarization erasing due to NBS. Our investigations provide a deep understanding of bias stress-induced instabilities in ALD-deposited ZnO FeFETs.