Jianyu Feng;Rong Fu;Yunqian Song;Qidong Wang;Chuan Chen;Liqiang Cao
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A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within \n<inline-formula> <tex-math>$2~^{\\circ }$ </tex-math></inline-formula>\nC. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. 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引用次数: 0
摘要
三维集成技术是扩展摩尔定律的有效解决方案,具有更好的性能和更高的密度。然而,三维集成中热点引起的温升问题会更加突出。本文通过提取微凸块层和带 TSV 芯片的等效热导率,提出了详细三维集成结构的等效分析模型。利用有限元仿真验证了等效的准确性,并利用该模型计算了热阻和预测了热点的最高温度。在三维集成中,第二传导路径可显著降低热点温度。本文提出了一种新的分析解决方案,用于计算热阻和预测三维集成中热点的最高温度。结果表明,所提出的热阻网络模型可以精确预测热点的温升。对于不同尺寸的热点,模拟与网络模型的误差仅在 2~^{\circ }$ C 范围内。作为芯片材料,金刚石能显著降低热点温度。此外,芯片厚度和微凸块层的热导率都会对不同大小的热点温度产生影响。对于大尺寸热点的情况,为降低热点温度,建议在封装时采用更小的微凸块和更大的芯片厚度。
The Analytical Model of Hotspot Temperature and the Effects of Different Factors in 3-D Integration
The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within
$2~^{\circ }$
C. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. For cases with large-sized hot spot, to decrease the hotspot temperature, smaller microbump and greater chip thickness are advised in packaging.
期刊介绍:
IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.