Sung-Ho Park;Jaehyeon Kim;Jonghyun Ko;Jiseong Im;Yeongheon Yang;Jae-Joon Kim;Jong-Ho Lee
{"title":"利用神经网络优化垂直 NAND 闪存的编程脉冲形状","authors":"Sung-Ho Park;Jaehyeon Kim;Jonghyun Ko;Jiseong Im;Yeongheon Yang;Jae-Joon Kim;Jong-Ho Lee","doi":"10.1109/LED.2024.3451430","DOIUrl":null,"url":null,"abstract":"We optimize the shape of the pulse to maximally increase threshold voltage (\n<inline-formula> <tex-math>${V}_{\\text {th}}\\text {)}$ </tex-math></inline-formula>\n during the incremental step pulse programming (ISPP) of vertical NAND (V-NAND) flash memory using neural networks (NNs). NN is trained using data on the increase in \n<inline-formula> <tex-math>${V}_{\\text {th}}$ </tex-math></inline-formula>\n of commercial V-NAND flash memory in response to randomly shaped programming pulses (PPs). The trained NN is utilized to optimize the shape of the PP. The principle behind the improvement in \n<inline-formula> <tex-math>${V}_{\\text {th}}$ </tex-math></inline-formula>\n increase due to the optimized PP, as well as the improvement results, are confirmed through measurements. When the optimized PP is applied to ISPP operation, it results in a 37% increase in ISPP slope. Furthermore, the optimized PP exhibits lower program disturbance, indicating the potential for faster programming with lower energy consumption.","PeriodicalId":13198,"journal":{"name":"IEEE Electron Device Letters","volume":"45 11","pages":"2102-2105"},"PeriodicalIF":4.1000,"publicationDate":"2024-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Optimization of Programming Pulse Shape for Vertical NAND Flash Memory Using Neural Networks\",\"authors\":\"Sung-Ho Park;Jaehyeon Kim;Jonghyun Ko;Jiseong Im;Yeongheon Yang;Jae-Joon Kim;Jong-Ho Lee\",\"doi\":\"10.1109/LED.2024.3451430\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We optimize the shape of the pulse to maximally increase threshold voltage (\\n<inline-formula> <tex-math>${V}_{\\\\text {th}}\\\\text {)}$ </tex-math></inline-formula>\\n during the incremental step pulse programming (ISPP) of vertical NAND (V-NAND) flash memory using neural networks (NNs). NN is trained using data on the increase in \\n<inline-formula> <tex-math>${V}_{\\\\text {th}}$ </tex-math></inline-formula>\\n of commercial V-NAND flash memory in response to randomly shaped programming pulses (PPs). The trained NN is utilized to optimize the shape of the PP. The principle behind the improvement in \\n<inline-formula> <tex-math>${V}_{\\\\text {th}}$ </tex-math></inline-formula>\\n increase due to the optimized PP, as well as the improvement results, are confirmed through measurements. When the optimized PP is applied to ISPP operation, it results in a 37% increase in ISPP slope. Furthermore, the optimized PP exhibits lower program disturbance, indicating the potential for faster programming with lower energy consumption.\",\"PeriodicalId\":13198,\"journal\":{\"name\":\"IEEE Electron Device Letters\",\"volume\":\"45 11\",\"pages\":\"2102-2105\"},\"PeriodicalIF\":4.1000,\"publicationDate\":\"2024-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Electron Device Letters\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10654387/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Electron Device Letters","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10654387/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
Optimization of Programming Pulse Shape for Vertical NAND Flash Memory Using Neural Networks
We optimize the shape of the pulse to maximally increase threshold voltage (
${V}_{\text {th}}\text {)}$
during the incremental step pulse programming (ISPP) of vertical NAND (V-NAND) flash memory using neural networks (NNs). NN is trained using data on the increase in
${V}_{\text {th}}$
of commercial V-NAND flash memory in response to randomly shaped programming pulses (PPs). The trained NN is utilized to optimize the shape of the PP. The principle behind the improvement in
${V}_{\text {th}}$
increase due to the optimized PP, as well as the improvement results, are confirmed through measurements. When the optimized PP is applied to ISPP operation, it results in a 37% increase in ISPP slope. Furthermore, the optimized PP exhibits lower program disturbance, indicating the potential for faster programming with lower energy consumption.
期刊介绍:
IEEE Electron Device Letters publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors.