利用双 k 隔板扩展铁电场效应晶体管的帕雷托前沿

IF 2.9 2区工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC

IEEE Transactions on Electron Devices Pub Date : 2024-08-23 DOI:10.1109/TED.2024.3443780

HyungMin Cho;HyunJoon Jeong;Yohan Kim;JinYoung Choi;Jeong-Taek Kong;SoYoung Kim

{"title":"利用双 k 隔板扩展铁电场效应晶体管的帕雷托前沿","authors":"HyungMin Cho;HyunJoon Jeong;Yohan Kim;JinYoung Choi;Jeong-Taek Kong;SoYoung Kim","doi":"10.1109/TED.2024.3443780","DOIUrl":null,"url":null,"abstract":"In this study, a novel dual-\n<italic>k\n spacer ferroelectric field-effect transistor (FeFET) structure is proposed. By adopting the dual-\n<italic>k\n spacer for the first time in FeFET, the target memory window (MW) of 0.5 V is achievable at a write voltage of 5 V. The write voltage shows a 2.0-V reduction from 7 V for the low-\n<italic>k\n spacer FeFET (L-FeFET) and a 1.0-V reduction from 6 V for the high-\n<italic>k\n spacer FeFET (H-FeFET). The write power of the proposed FeFET was 25.9% lower than that of the low-\n<italic>k\n FeFET and H-FeFET. These improvements significantly expand the Pareto front and mitigate the effects of trapped charge. The dual-\n<italic>k\n spacer FeFET structure is a promising candidate for low-voltage and low-power operations.","PeriodicalId":13092,"journal":{"name":"IEEE Transactions on Electron Devices","volume":null,"pages":null},"PeriodicalIF":2.9000,"publicationDate":"2024-08-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Expanding the Pareto Front of Ferroelectric Field-Effect Transistors With a Dual-k Spacer\",\"authors\":\"HyungMin Cho;HyunJoon Jeong;Yohan Kim;JinYoung Choi;Jeong-Taek Kong;SoYoung Kim\",\"doi\":\"10.1109/TED.2024.3443780\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this study, a novel dual-\\n<italic>k\\n spacer ferroelectric field-effect transistor (FeFET) structure is proposed. By adopting the dual-\\n<italic>k\\n spacer for the first time in FeFET, the target memory window (MW) of 0.5 V is achievable at a write voltage of 5 V. The write voltage shows a 2.0-V reduction from 7 V for the low-\\n<italic>k\\n spacer FeFET (L-FeFET) and a 1.0-V reduction from 6 V for the high-\\n<italic>k\\n spacer FeFET (H-FeFET). The write power of the proposed FeFET was 25.9% lower than that of the low-\\n<italic>k\\n FeFET and H-FeFET. These improvements significantly expand the Pareto front and mitigate the effects of trapped charge. The dual-\\n<italic>k\\n spacer FeFET structure is a promising candidate for low-voltage and low-power operations.\",\"PeriodicalId\":13092,\"journal\":{\"name\":\"IEEE Transactions on Electron Devices\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.9000,\"publicationDate\":\"2024-08-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Transactions on Electron Devices\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10645796/\",\"RegionNum\":2,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q2\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Transactions on Electron Devices","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10645796/","RegionNum":2,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

引用次数: 0

摘要

本研究提出了一种新型双 k 间距铁电场效应晶体管 (FeFET) 结构。通过首次在铁电场效应晶体管中采用双 k 间距，可在 5 V 写入电压下实现 0.5 V 的目标存储窗口 (MW)。低 k 值间隔 FeFET（L-FeFET）的写入电压比 7 V 降低了 2.0 V，而高 k 值间隔 FeFET（H-FeFET）的写入电压比 6 V 降低了 1.0 V。拟议的 FeFET 的写入功率比低 k FeFET 和 H-FeFET 低 25.9%。这些改进大大扩展了帕累托前沿，并减轻了陷波电荷的影响。双 k 间距 FeFET 结构是低电压和低功耗操作的理想候选器件。

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Expanding the Pareto Front of Ferroelectric Field-Effect Transistors With a Dual-k Spacer

In this study, a novel dual- k spacer ferroelectric field-effect transistor (FeFET) structure is proposed. By adopting the dual- k spacer for the first time in FeFET, the target memory window (MW) of 0.5 V is achievable at a write voltage of 5 V. The write voltage shows a 2.0-V reduction from 7 V for the low- k spacer FeFET (L-FeFET) and a 1.0-V reduction from 6 V for the high- k spacer FeFET (H-FeFET). The write power of the proposed FeFET was 25.9% lower than that of the low- k FeFET and H-FeFET. These improvements significantly expand the Pareto front and mitigate the effects of trapped charge. The dual- k spacer FeFET structure is a promising candidate for low-voltage and low-power operations.

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来源期刊

IEEE Transactions on Electron Devices 工程技术-工程：电子与电气

CiteScore

5.80

自引率

16.10%

发文量

937

审稿时长

3.8 months

期刊介绍： IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.