模拟集成多回路 LDO：从分析到设计

IF 2.6 3区工程技术 Q2 COMPUTER SCIENCE, INFORMATION SYSTEMS

Electronics Pub Date : 2024-09-11 DOI:10.3390/electronics13183602

Konstantinos Koniavitis, Vassilis Alimisis, Nikolaos Uzunoglu, Paul P. Sotiriadis

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引用次数: 0

摘要

本文介绍了一种多环路稳定低压差稳压器，其直流电源抑制比为 85 dB，相位裕度为 80°。它适用于低功耗、低电压和节省面积的应用，因为其功耗低于 100 μA。压降电压仅为 400 mV，电源轨电压为 1 V。此外，在电路验证之前，还对稳定性和噪声进行了全面的数学分析。为确认实现过程的正常运行，还提取了电压和温度角变化模拟。所提议的稳压器是在 TSMC 90 纳米 CMOS 工艺中利用 Cadence IC Suite 设计和验证的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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An Analog Integrated Multiloop LDO: From Analysis to Design

This paper introduces a multiloop stabilized low-dropout regulator with a DC power supply rejection ratio of 85 dB and a phase margin of 80°. It is suitable for low-power, low-voltage and area-efficient applications since it consumes less than 100 μA. The dropout voltage is only 400 mV and the power supply rails are 1 V. Furthermore, a full mathematical analysis is conducted for stability and noise before the circuit verification. To confirm the proper operation of the implementation process, voltage and temperature corner variation simulations are extracted. The proposed regulator is designed and verified utilizing the Cadence IC Suite in a TSMC 90 nm CMOS process.

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来源期刊

Electronics Computer Science-Computer Networks and Communications

CiteScore

1.10

自引率

10.30%

发文量

3515

审稿时长

16.71 days

期刊介绍： Electronics (ISSN 2079-9292; CODEN: ELECGJ) is an international, open access journal on the science of electronics and its applications published quarterly online by MDPI.