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引用次数: 0
摘要
集成电路很容易因静电放电(ESD)而损坏,因此集成电路必须采用 ESD 保护电路。在某些应用中,内部电路可能采用全 n 型晶体管设计。在这种情况下,ESD 保护电路应只使用 n 型晶体管,以减少所需的工艺掩膜数量。本研究提出了全 MOS 电源轨 ESD 管钳的基本设计和改进设计。改进设计使用了电流镜电路和 nMOS 串,以分别减少芯片面积和漏电。这些 ESD 保护电路已在 0.18 英寸 CMOS 工艺中实现并通过验证。所提出的设计具有成本效益,并能为实际应用提供更高的 ESD 鲁棒性。
All-nMOS Power-Rail ESD Clamp Circuit With Compact Area and Low Leakage
ICs are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all n-type transistor design. In such cases, the ESD protection circuit should only use n-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-nMOS power-rail ESD clamp. The improved design uses a current mirror circuit and nMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18-
$\mu $
m CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.
期刊介绍:
IEEE Transactions on Electron Devices publishes original and significant contributions relating to the theory, modeling, design, performance and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanoelectronics, optoelectronics, photovoltaics, power ICs and micro-sensors. Tutorial and review papers on these subjects are also published and occasional special issues appear to present a collection of papers which treat particular areas in more depth and breadth.