非共面铜柱存在时压力对芯片堆栈结构稳定性的影响

IF 2.3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC
Yu Li;Li Liu;Meng Ruan;Zhengzhi Wang;Sheng Liu;Zhiwen Chen
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引用次数: 0

摘要

铜-铜键合广泛应用于芯片互连的三维堆叠。然而,铜柱的非共面性会严重影响堆叠芯片的可靠性。在这项工作中,我们通过有限元建模和分子动力学(MDs)模拟研究了键合压力对非共面铜柱芯片堆叠的影响。通过有限元建模,TSV 中的最大残余应力位于离芯片中心最远的底部铜柱,并随着键合压力的增加而增加。研究还发现,整体翘曲最初随芯片层数的增加而线性增加,当铜柱不共面时,整体翘曲趋于稳定。线性增加率随着键合压力的增加而增加。根据 MDs 模拟,短柱中的键合层厚度随着键合时间和压力的增加而持续增加。相比之下,标准支柱的厚度随着时间的推移而增加,并最终趋于稳定。在此期间,键合压力对标准柱中键合层厚度的影响微乎其微,位错一般集中在键合层附近,成为铜原子扩散到键合层的通道。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impacts of Pressure on the Stability of Chip Stack Structures in the Presence of Noncoplanar Cu Pillars
Cu-Cu bonding is widely used in 3-D stacking for chip interconnection. However, noncoplanarity of Cu pillars can significantly influence the reliability of the stacked chips. In this work, the impacts of bonding pressures on chip stacking with noncoplanar Cu pillars were investigated through finite element modeling and molecular dynamics (MDs) simulations. From finite element modeling, the maximum residual stress in the TSV was located in the bottom Cu pillar furthest from the center of the chip and increased with bonding pressure. It was also found that the overall warpage increased linearly with the number of chip layers initially and then stabilized when Cu pillars were noncoplanar. The linear increase rate raised with higher bonding pressure. Based on MDs simulations, the thickness of bonding layer in the shorter pillar increased continuously with bonding time and pressure. In contrast, the thickness in standard pillars grew over time and eventually stabilized. During this, the bonding pressure posed negligible effects on the bonding layer thickness in standard pillars, and dislocations were generally concentrated near the bonding layer, serving as channels for Cu atom diffusion into the bonding layer.
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来源期刊
IEEE Transactions on Components, Packaging and Manufacturing Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
4.70
自引率
13.60%
发文量
203
审稿时长
3 months
期刊介绍: IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.
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