用于低功耗嵌入式应用的基于带对带隧道技术的统一 RAM (URAM)

IF 2.1 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Avinash Lahgere;Alok Kumar Kamal;Rishu Kumar
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引用次数: 0

摘要

在这篇文章中,我们报告了一种基于隧道场效应晶体管(TFET)的统一随机存取存储器(T-URAM),它将非易失性存储器(NVM)和单晶体管(1T)DRAM 集成到单个 TFET 器件中。与之前发布的 URAM 不同,拟议的 T-URAM 利用带对带隧道 (BTBT) 传导对 NVM 和 1T DRAM 进行编程。这种方法有两大优势:低电源电压要求和无干扰 NVM 操作。此外,T-URAM 还通过 NVM 和 1T DRAM 的独立栅极确保无干扰的存储器操作。仿真显示,与现有的 URAM 相比,T-URAM 所需的电源电压降低了 1.5 到 4.5 倍。在 358 K 时,T-URAM 在 1T DRAM 模式下的保留时间(RT)为 500 ms,分别比埋入 n 孔的 bulk FinFET URAM 和 ITRS 预测值高出 62.5 倍和 7.8 倍。对于 NVM 模式,栅极长度为 50 nm 时的 RT 与之前报告的 URAM 一致。在 358 K 的 1T DRAM 模式下,T-URAM 的感应裕度约为 1.9 $/$mu$A/$mu$m,比基于 TFT 的 URAM 高出约 7.6 倍。我们还提出了使用 T-URAM 实现 2x2 交叉条存储器阵列的方案。这些发现为设计未来应用的低功耗、多用途嵌入式存储器铺平了道路。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Band-to-Band Tunneling Based Unified RAM (URAM) for Low Power Embedded Applications
In this article, we have reported a tunnel field-effect transistor (TFET) based unified random access memory (T-URAM), integrating nonvolatile memory (NVM) and single transistor (1T) DRAM into a single TFET device. Unlike previously published URAMs, the proposed T-URAM utilizes band-to-band tunneling (BTBT) conduction for programming both NVM and 1T DRAM. This approach offers two main advantages: low supply voltage requirements and disturbance-free NVM operation. Additionally, T-URAM ensures interference-free memory operation through separate gates for NVM and 1T DRAM. Simulations show that T-URAM requires 1.5× to 4.5× less supply voltage compared to existing URAMs. At 358 K, the retention time (RT) of T-URAM in 1T DRAM mode is 500 ms, which is $\sim$ 62.5× and $\sim$ 7.8× higher than the buried n-well bulk FinFET URAM and ITRS prediction, respectively. For NVM mode, the RT at a gate length of 50 nm matches that of previously reported URAMs. The sense margin of T-URAM in 1T DRAM mode at 358 K is about 1.9 $\mu$ A/ $\mu$ m, which is roughly 7.6× higher than TFT-based URAM. We also propose a 2x2 crossbar memory array implementation using T-URAM. These findings pave the way for designing low-power, multi-purpose embedded memory for future applications.
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来源期刊
IEEE Transactions on Nanotechnology
IEEE Transactions on Nanotechnology 工程技术-材料科学:综合
CiteScore
4.80
自引率
8.30%
发文量
74
审稿时长
8.3 months
期刊介绍: The IEEE Transactions on Nanotechnology is devoted to the publication of manuscripts of archival value in the general area of nanotechnology, which is rapidly emerging as one of the fastest growing and most promising new technological developments for the next generation and beyond.
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