Double π-gate AlGaN/GaN HEMT with reduced surface and buffer traps and enhanced reliability

A double π-gate engineering technique is proposed to analyse the device performance and enhance the reliability by reducing the surface traps and buffer traps using Silvaco TCAD simulator tool. Peak electric field due to V_gs, under the gate can worse the device performance and cause memory effects. The peak electric field destructs the charge carrier density (2-DEG) in the channel, lowers the charge carrier density in the channel and results in current collapse. The peak electric field make the electrons/holes (in n-type/p-type) to get energized (hot electron) and injected into buffer region and other epi-layers by the process trapping/de-trapping. Drain current collapse (∆ I_dmax) and threshold voltage shift (∆V_th) occur due to trapping/de-trapping. Proposed method has T-gate which is spilt into 3-pillars referred to as double-π shaped gate structure. Results obtained from the suggested technique showed that perfect peak current in the channel and uniform electric field distribution is achieved. The dc characteristics pulsed I-V, pulsed C-V, and pulsed S-parameters are analysed to study the trapping effects.