用于 14/16 纳米技术节点 SoC 的低压和高压 FinFET 的小信号和大信号射频特性分析与建模

IF 2 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC
Anirban Kar;Shivendra Singh Parihar;Jun Z. Huang;Huilong Zhang;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan
{"title":"用于 14/16 纳米技术节点 SoC 的低压和高压 FinFET 的小信号和大信号射频特性分析与建模","authors":"Anirban Kar;Shivendra Singh Parihar;Jun Z. Huang;Huilong Zhang;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan","doi":"10.1109/JEDS.2024.3384008","DOIUrl":null,"url":null,"abstract":"Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.","PeriodicalId":13210,"journal":{"name":"IEEE Journal of the Electron Devices Society","volume":null,"pages":null},"PeriodicalIF":2.0000,"publicationDate":"2024-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10488034","citationCount":"0","resultStr":"{\"title\":\"Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs\",\"authors\":\"Anirban Kar;Shivendra Singh Parihar;Jun Z. Huang;Huilong Zhang;Weike Wang;Kimihiko Imura;Yogesh Singh Chauhan\",\"doi\":\"10.1109/JEDS.2024.3384008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.\",\"PeriodicalId\":13210,\"journal\":{\"name\":\"IEEE Journal of the Electron Devices Society\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":2.0000,\"publicationDate\":\"2024-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10488034\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Journal of the Electron Devices Society\",\"FirstCategoryId\":\"5\",\"ListUrlMain\":\"https://ieeexplore.ieee.org/document/10488034/\",\"RegionNum\":3,\"RegionCategory\":\"工程技术\",\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"Q3\",\"JCRName\":\"ENGINEERING, ELECTRICAL & ELECTRONIC\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Journal of the Electron Devices Society","FirstCategoryId":"5","ListUrlMain":"https://ieeexplore.ieee.org/document/10488034/","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0

摘要

现代片上系统 (SoC) 架构需要具有出色数字、模拟和射频 (RF) 特性的低压 (LV) 核心晶体管,以及用作稳健 I/O 缓冲器的厚氧化物晶体管和对高效电源管理至关重要的高压 (HV) 晶体管。本研究针对采用 14/16 纳米技术的商用低压和高压鳍式场效应晶体管 (FinFET) 介绍了全面的直流到射频特性分析、详细的建模策略以及随后的模型参数提取。对行业标准 BSIM-CMG 紧凑型模型进行了修改,以准确捕捉与数字 LV FinFET 集成在 SoC 应用中的 HV FinFET 器件的特性。与当代平面 CMOS 技术相比,对 LV、I/O 和 HV FinFET 的直流、模拟和射频性能进行了详细分析。使用开发的模型评估了器件的大信号性能,并通过测量数据进行了验证。最后,还简要概述了与建模器件相关的性能指标。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Small-Signal and Large-Signal RF Characterization and Modeling of Low and High Voltage FinFETs for 14/16 nm Technology Node SoCs
Modern System-on-Chip (SoC) architectures necessitate low-voltage (LV) core transistors featuring excellent digital, analog, and radio frequency (RF) properties, as well as thick oxide transistors serving as robust I/O buffers and high-voltage (HV) transistors essential for efficient power management. This study presents a comprehensive DC to RF characterization, a detailed modeling strategy, and subsequent model parameter extraction for commercially produced LV and HV Fin Field Effect Transistors (FinFETs) at 14/16 nm technology. The industry-standard BSIM-CMG compact model is modified to accurately capture the characteristics of the HV FinFET devices integrated with the digital LV FinFETs for SoC applications. A detailed analysis of the DC, analog, and RF performance of LV, I/O, and HV FinFETs compared to the contemporary planar CMOS technology is performed. The large-signal performance of the device is evaluated using the developed model and validated with the measured data. Finally, a concise overview of the performance indicators associated with the modeled device is also presented.
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来源期刊
IEEE Journal of the Electron Devices Society
IEEE Journal of the Electron Devices Society Biochemistry, Genetics and Molecular Biology-Biotechnology
CiteScore
5.20
自引率
4.30%
发文量
124
审稿时长
9 weeks
期刊介绍: The IEEE Journal of the Electron Devices Society (J-EDS) is an open-access, fully electronic scientific journal publishing papers ranging from fundamental to applied research that are scientifically rigorous and relevant to electron devices. The J-EDS publishes original and significant contributions relating to the theory, modelling, design, performance, and reliability of electron and ion integrated circuit devices and interconnects, involving insulators, metals, organic materials, micro-plasmas, semiconductors, quantum-effect structures, vacuum devices, and emerging materials with applications in bioelectronics, biomedical electronics, computation, communications, displays, microelectromechanics, imaging, micro-actuators, nanodevices, optoelectronics, photovoltaics, power IC''s, and micro-sensors. Tutorial and review papers on these subjects are, also, published. And, occasionally special issues with a collection of papers on particular areas in more depth and breadth are, also, published. J-EDS publishes all papers that are judged to be technically valid and original.
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